Product Name: FMC6678 Product ID: Project ID:
IISC-6678 Board Hardware Design Manual
Acronyms Terms Definition DDR3 Double Data Rate 3 Interface DSP Digital Signal Processor EEPROM Electrically Erasable Programmable Read Only Memory EMIF External Memory Interface FPGA Field Programmable Gate Array RFU Reserved for Future Use I2C Inter Integrated Circuit JTAG Joint Test Action Group LED Light Emitting Diode PCIE PCI express SDRAM Synchronous Dynamic Random Access Memory SERDES Serializer-Deserializer SGMII Serial Gigabit Media Independent Interface SRIO Serial RapidIO UART Universal Asynchronous Receiver/Transmitter
China Research Development Center for Internet of Things
Institute of Microelectronics, Chinese Academy of Sciences Information Identification & System Control Research Center
2014-5-8
Information Identification & System Control Research Center
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Table of Contents
1. Overview ....................................................................................................................................... 1
1.1 Key Features ....................................................................................................................... 1 1.2 Functional Overview ........................................................................................................... 2 1.3 Basic Operation ................................................................................................................... 2 1.4 Boot Mode and Boot Configuration Switch Setting ........................................................... 3 1.5 Power Supply ...................................................................................................................... 3 2. Introduction to the IISC-6678 Board ............................................................................................ 5
2.1 IISC-6678 Board Boot Mode and Boot Configuration Switch Settings ............................. 5 2.2 JTAG - Emulation Overview ............................................................................................... 6 2.3 Clock Domains .................................................................................................................... 6 2.4 I2C Boot EEPROM / SPI NOR Flash.................................................................................. 7 2.5 UART .................................................................................................................................. 8 2.6 FPGA .................................................................................................................................. 8 2.7 Gigabit Ethernet Connections ............................................................................................. 9 2.8 Serial RapidIO (SRIO) Interface ......................................................................................... 9 2.9 DDR3 External Memory Interface .................................................................................... 10 2.10 16-bit Asynchronous External Memory Interface (EMIF-16) ......................................... 10 2.11 HyperLink Interface ........................................................................................................ 11 2.12 PCIe Interface ................................................................................................................. 11 2.13 FMC Interface ................................................................................................................. 12 3. IISC-6678 Board Physical Specifications ................................................................................... 14
3.1 Board Layout..................................................................................................................... 14 3.2 Connector Index ................................................................................................................ 16
3.2.1 EMU1& DSP_JTAG, TI 60-Pin &DSP_JTAG Connector .................................. 16 3.2.2 JP2, FAN Connector ............................................................................................ 18 3.2.3 J1, HyperLink Connector .................................................................................... 18 3.2.4 T1、T2, Ethernet Connector ............................................................................... 19 3.2.5 TAP_FPGA1, FPGA JTAG Connector (For Factory Use Only) ......................... 20 3.2.6 J3, FMC (FPGA Mezzanine Card) Connector .................................................... 20 3.3 DIP and Pushbutton Switches ........................................................................................... 26
3.3.1 RST_FULL1, Full Reset ..................................................................................... 26 3.3.2 RST_COLD1, Cold Reset ................................................................................... 26 3.3.3 RST_WARM1, Warm Reset ................................................................................ 26 3.3.4 SW2, SW3, SW4 and SW5, DSP boot mode and Configuration ........................ 26 3.3.5 SW6, DSP PCIESS Enable and User Defined Switch Configuration ................. 27 3.4 System LEDs..................................................................................................................... 27 4. System Power Requirements....................................................................................................... 29
4.1 Power Requirements ......................................................................................................... 29 4.2 The Power Supply Distribution ......................................................................................... 30 4.3 The Power Supply Boot Sequence .................................................................................... 31 5. IISC-6678 Board FPGA Function Description ........................................................................... 32
5.1 FPGA overview ................................................................................................................. 32
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IISC-6678 Board Hardware Design Manual May. 8th 2014
5.2 FPGA signals description .................................................................................................. 32 5.3 Sequence of operation ....................................................................................................... 37
5.3.1 Power on Sequence ............................................................................................. 37 5.3.2 Power off Sequence ............................................................................................. 37 5.4 Reset definition ................................................................................................................. 38
5.4.1 Reset Behavior .................................................................................................... 38 5.4.2 Reset Switches and Triggers ............................................................................... 38
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IISC-6678 Board Hardware Design Manual May. 8th 2014
1. Overview
This chapter provides an overview of the IISC-6678 along with the key features and block diagram. 1.1 Key Features 1.2 Functional Overview 1.3 Basic Operation
1.4 Configuration Switch Settings 1.5 Power Supply
1.1 Key Features
The IISC-6678 Board is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop applications for the Texas Instruments‟ TMS320C6678 Digital Signal Processor (DSP). The IISC-6678 Board also serves as a hardware reference design platform for the TMS320C6678 DSP. Schematics, code examples and application notes are available to ease the hardware development process and to reduce the time to market. The key features of the IISC-6678 Board are:
Texas Instruments' multi-core DSP – TMS320C6678 512 Mbytes of DDR3-1333 Memory 64 Mbytes of NAND Flash 16MB SPI NOR FLASH
Two Gigabit Ethernet ports supporting 10/100/1000 Mbps data-rate and one
RJ45/RS232
160 pin LPC FMC Interface containing SRIO, PCIe, LVDS and Power Supply High Performance connector for HyperLink connector 128K-byte I2C EEPROM for booting
User LEDs, 5 Banks of DIP Switches and 4 Software-controlled LEDs TI 60-Pin JTAG header to support all external emulator types Powered by DC power-brick adapter (5V/8.0A)
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IISC-6678 Board Hardware Design Manual May. 8th 2014
1.2 Functional Overview
The TMS320C66x™ DSPs (including the TMS320C6678 device) are the highest-performance fixed / floating-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6678device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), designed specifically for high density wireline / wireless media gateway infrastructure. It is an ideal solution for IP border gateways, video transcoding and translation, video-server and intelligent voice and video recognition applications. The C66x devices are backward code-compatible from previous devices that are part of the C6000™ DSP platform.
The functional block diagram of IISC-6678 Board is shown in the figure below:
Figure 1.1 Block Diagram of IISC-6678 Board
1.3 Basic Operation
The IISC-6678 platform is designed to work with TI‟s Code Composer Studio (CCS) development environment and ships with a version specifically tailored for this board. CCS can interface with the board through an external emulator.
To start operating the board, follow instructions in the Quick Start Guide，to install all the necessary development tools, drivers and documentation.
After the installation has completed, follow the steps below to run Code Composer
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Studio.
1. Connect USB cable from host PC to IISC-6678 Board.
2. Power-on the board using the power brick adapter (5V/8.0A) supplied along with this IISC-6678 Board.
3. Launch Code Composer Studio from host PC by double clicking on its icon on the PC desktop.
Figure 1.2 IISC-6678 Board Layout
1.4 Boot Mode and Boot Configuration Switch Setting
The IISC-6678 Board has 20 sliding DIP switches (Board Ref. SW2 to SW6) to determine boot mode, boot configuration, device number, Endian mode, CorePac PLL clock selection and PCIe Mode selection options latched at reset by the DSP.
1.5 Power Supply
The IISC-6678 Board can be powered from a single +5V / 8.0A DC (40W) external power supply connected to the DC power jack (JP1). Internally, +5V input is converted into required voltage levels using local DC-DC converters. DSPA_CVDD (+0.90V~+1.1V) used for the DSP Core logic
VCC1V0 is used for DSP internal memory and HyperLink/SRIO/SGMII/PCIe
SERDES termination of DSP
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IISC-6678 Board Hardware Design Manual May. 8th 2014
VCC1V5 is used for DDR3 buffers of DSP, HyperLink/SRIO/SGMII/PCIe
SERDES regulators in DSP and DDR3 DRAM chips
VCC1V8 is used for DSP PLLs, DSP LVCMOS I/Os and FPGA I/Os driving the
DSP
+1.8V is used for FPGA I/Os driving the DSP +2.5V is used for Gigabit Ethernet PHY core
+1.2V is used for FPGA core and Gigabit Ethernet PHY core
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IISC-6678 Board Hardware Design Manual May. 8th 2014
2. Introduction to the IISC-6678 Board
This chapter provides an introduction and details of interfaces for the IISC-6678 Board. It contains:
2.1 IISC-6678 Board Boot mode and Boot configuration switch settings 2.2 JTAG - Emulation Overview 2.3 Clock Domains
2.4 I2C boot EEPROM / SPI NOR Flash 2.5 UART 2.6 FPGA
2.7 Gigabit Ethernet PHY
2.8 Serial RapidIO (SRIO) Interfaces 2.9 DDR3 External Memory Interfaces
2.10 16-bit Asynchronous External Memory Interface 2.11 HyperLink Interface 2.12 PCIe Interface 2.13 FMC Interface
2.1 IISC-6678 Board Boot Mode and Boot Configuration Switch Settings
The IISC-6678 Board has five configuration DIP switches: SW2, SW3, SW4, SW5 and SW6 that contain 17 individual values latched when reset is released. This occurs when power is applied the board, after the user presses the FULL_RESET push button.
SW2 determines general DSP configuration, little or Big Endian mode and boot device selection.
SW3, SW4, SW5 and SW6 determine DSP boot device configuration, CorePac PLL setting and PCIe mode selection and enable.
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Figure 2.1 IISC-6678 Board Boot Mode and Configuration
2.2 JTAG - Emulation Overview
The TI 60-pin JTAG header (EMU1) is provided for high speed real-time emulation. The TI 60-pin JTAG supports all standard TI DSP emulators. An adapter will be required for use with some emulators.
The second way of accessing the DSP is through the DSP_JTAG port.
The JTAG interface among the DSP, external emulator and DSP_JTAG connector is shown in the below figure.
Figure 2.2 IISC-6678 Board JTAG emulation
2.3 Clock Domains
The IISC-6678 Board incorporates a variety of clocks to the TMS320C6678 as well
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IISC-6678 Board Hardware Design Manual May. 8th 2014
as other devices which are configured automatically during the power up configuration sequence. The figure below illustrates clocking for the system in the IISC-6678 Board module.
Figure 2.3 IISC-6678 Board Clock Domains
2.4 I2C Boot EEPROM / SPI NOR Flash
The I2C modules on the TMS320C6678 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface. The I2C bus is connected to one EEPROM.
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on TMS320C6678 is supported only in Master mode.
The NOR FLASH attached to CS0z on the TMS320C6678 is a NUMONYX N25Q128A21. This NOR FLASH size is 16MB. It can contain demonstration programs such as POST or the OOB demonstration. The CS1z of the SPI is used by the DSP to access registers within the FPGA.
Figure 2.4 IISC-6678 Board SPI/EEPROM Connections
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IISC-6678 Board Hardware Design Manual May. 8th 2014
2.5 UART
The figure 2.5 illustrates the UART connections on the IISC-6678 Board.
Figure 2.5 IISC-6678 Board UART Connections
2.6 FPGA
The FPGA (Xilinx XC3S200AN) controls the reset mechanism of the DSP and provides boot mode and boot configuration data through SW2, SW3, SW4, SW5 and SW6. The FPGA also supports 4 user LEDs and 1 user switch through control registers.
All FPGA registers are accessible over the SPI interface.
The figure below shows the interface between TMS320C6678 DSP and FPGA.
Figure 2.6 IISC-6678 Board FPGA Connections
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IISC-6678 Board Hardware Design Manual May. 8th 2014
2.7 Gigabit Ethernet Connections
The IISC-6678 Board provides connectivity for both SGMII Gigabit Ethernet ports. These are shown in figure below:
Figure 2.7 IISC-6678 Board Ethernet Routing
The Ethernet PHY is connected to DSP EMAC to provide a copper interface and routed to a Gigabit RJ-45 connector.
2.8 Serial RapidIO (SRIO) Interface
The IISC-6678 Board supports high speed SERDES based Serial RapidIO (SRIO) interface.
There are total 4 RapidIO ports available on TMS320C6678. All SRIO ports are routed to FMC edge connector on board. Below figure shows RapidIO connections between the DSP and FMC edge connector.
Figure 2.8 IISC-6678 Board SRIO Port Connections
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IISC-6678 Board Hardware Design Manual May. 8th 2014
2.9 DDR3 External Memory Interface
The TMS320C6678 DDR3 interface connects to five 1Gbit (64Meg x 16) DDR3 1333 devices.
This configuration allows the use of both “narrow (16-bit)”, “normal (32-bit)”, and “wide (64-bit)” modes of the DDR3 EMIF.
SAMSUNG DDR3 K4B1G1646x-HCH9 SDRAMs (64Mx16; 667MHz) are used on the DDR3 EMIF.
The figure 2.9 illustrates the implementation for the DDR3 SDRAM memory.
Figure 2.9 IISC-6678 Board SDRAM
2.10 16-bit Asynchronous External Memory Interface (EMIF-16)
The TMS320C6678 EMIF-16 interface connects to one 512Mbit (64MB) NAND flash device on the IISC-6678 Board. The EMIF16 module provides an interface between DSP and asynchronous external memories such as NAND and NOR flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide (literature number SPRUGZ3).
NUMONYX_NAND512R3A2SZA6ENAND flash (64MB) is used on the EMIF-16. The figure 2.10 illustrates the EMIF-16 connections on the IISC-6678 Board.
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Figure 2.10 IISC-6678 Board EMIF-16 connections
2.11 HyperLink Interface
The TMS320C6678 provides the HyperLink bus for companion chip/die interfaces. This is a four lane SerDes interface designed to operate at 12.5 Gbps per lane. The interface is used to connect with external accelerators.
The interface includes the Serial Station Management Interfaces used to send power management and flow messages between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output buses and two 2-wire input buses.
Each 2-wire bus includes a data signal and a clock signal.
The figure 2.11 illustrates the Hyperlink bus connections on the IISC-6678 Board.
Figure 2.11 IISC-6678 Board HyperLink connections
2.12 PCIe Interface
The 2 lane PCI express (PCIe) interface on IISC-6678 Board provides a connection
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IISC-6678 Board Hardware Design Manual May. 8th 2014
between the DSP and FMC connector. The PCI Express interface provides low pin count, high reliability, and high-speed data transfer at rates of 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide (literature number SPRUGS6). The IISC-6678 Board provides the PCIe connectivity to FMC backplane on the IISC-6678Board;this is shown in figure 2.12.
Figure 2.12 IISC-6678 Board PCIe Port Connections
2.13 FMC Interface
The FMC (FPGA Mezzanine Card) standard describes a versatile module, which can target a range of applications, environments, and markets. The specification defines a commercial grade version, which extends to cover a ruggedized conduction variant. The specification of the double width modules helps applications that need additional carrier card bandwidth, greater front panel space, or a larger PCB area.
In the design of FMC module, fixed telecommunication number location, using minimal system support and flexible pin allocation, to minimize design effort and resources, not only improve the efficiency, but also brought many significant advantages, mainly has following several aspects:
(1) Design reuse: whether the design of the internal plate with custom and commercial product (COTS) sub card or the card loading, FMC standard contributes to the existing FPGA / carrier card design to use the new I/O, which only needs to replace the FMC module and slightly adjust the FPGA design.
(2) Data throughput: support the signal transmission rate up to 10 Gb/s, between the sub card and carrier card own the potential total bandwidth of 40 Gb/s.
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IISC-6678 Board Hardware Design Manual May. 8th 2014
(3) I/O: provide sufficient number of I/O, closely spaced, occupy less space
(4) Compatibility: the power standard, signal definition standard, increase mutual compatibility
(5) Stability: wide area contact, using the BGA package, increase the seismic performance
The figure 2.13 illustrates the FMC Interface connections on the IISC-6678 Board.
Figure 2.13 IISC-6678 Board FMC connections
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IISC-6678 Board Hardware Design Manual May. 8th 2014
3. IISC-6678 Board Physical Specifications
This chapter describes the physical layout of the IISC-6678 Board and its connectors, switches and test points. It contains: 3.1 Board Layout 3.2 Connector Index 3.3 Switches 3.4 System LEDs
3.1 Board Layout
The IISC-6678 Board dimension is 170mm x 80mm. It is a 12-layer board and powered through connector JP1. Figure 3.1 and 3.2 shows package layout of the IISC-6678 Board, figure 3.3 and 3.4 shows board geometry of the IISC-6678.
Figure 3.1 IISC-6678 Board Package Layout – TOP view
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Figure 3.2 IISC-6678 Board Package Layout – BOTTOM view
Figure 3.3 IISC-6678 Board Geometry – TOP view
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Figure 3.4 IISC-6678 Board Geometry – Bottom view
3.2 Connector Index
The IISC-6678 Board has several connectors which provide access to various interfaces on the board.
Table 3.1 IISC-6678 Board Connector Description Connector Pins 2 2 36 13 60 18 18 6 160 9 9 Function DC Power Input Jack Connector FAN connector for +5V DC FAN JP1 JP2 J1 DSP_JTAG EMU1 T1 T2 TAP_JTAG1 J3 P4 P3 HyperLink connector for companion chip/die interface External JTAG Connector TI 60-Pin DSP JTAG Connector Gigabit Ethernet RJ-45 Connector Gigabit Ethernet RJ-45 Connector FPGA JTAG Connector FMC (FPGA Mezzanine Card) Connector Extend IO Connector UART Connector 3.2.1 EMU1& DSP_JTAG, TI 60-Pin &DSP_JTAG Connector
EMU1 is a high speed system trace capable TI 60-pin JTAG connector for
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IISC-6678 Board Hardware Design Manual May. 8th 2014
XDS560V2 type of DSP emulation. Whenever an external emulator is plugged into EMU1, the external emulator connection will be switched to the DSP. The I/O voltage level on these pins is 1.8V. So any 1.8 V level compatible emulators can be used to interface with the TMS320C6678 DSP.
The pin out for the EMU1 connector is shown in figure below:
Table 3.2 EMU1 Connector pin out Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Signal Name GND GND GND GND GND GND GND Type0(NC) GND GND GND GND GND GND TRGRST# ID0(GND) TMD EMU17 TDI EMU14 EMU12 TDO TVD(+1.8V) EMU9 EMU7 EMU5 TCK EMU2 EMU0 ID1(GND) Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Signal Name ID2(GND) EMU18 TRST# EMU16 EMU15 EMU13 EMU11 TCK EMU10 EMU8 EMU6 EMU4 EMU3 EMU1 ID3(GND) NC GND GND GND GND GND GND Type1(GND) GND GND GND GND GND GND GND
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IISC-6678 Board Hardware Design Manual May. 8th 2014
The pin out for the DSP_JTAG connector is shown in figure below:
Table 3.3 DSP_JTAG Connector pin out Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Signal Name TMS TRST TDI GND VCC NC TDO GND TCKR GND TCK GND EMU0 EMU1 3.2.2 JP2, FAN Connector
The IISC-6678 Board incorporates a dedicated cooling fan. The fan selected provides maximum cooling (CFM) and operates on 5V DC. JP2 will be connected to provide 5V DC to the fan.
Table 3.4 JP2 Connector pin out Pin 1 2 Signal Name 5V GND 3.2.3 J1, HyperLink Connector
The IISC-6678 Board provides a HyperLink connection by a mini-SAS HD+ 4i connector. The connector contains 8 SERDES pairs and 4 sideband sets to carry full HyperLink signals. The connector is shown in Figure 3.5and its pin out is shown in Table 3.8. This connector is the Molex iPass+HD connector 76867-0011.
Table 3.5 The HyperLink Connector Pin A1 A2 A3 A4 A5 A6 Signal Name HyperLink_TXFLCLK HyperLink_RXFLCLK GND HyperLink_RXP1 HyperLink_RXN1 GND Pin C1 C2 C3 C4 C5 C6 Signal Name HyperLink_TXPMDAT HyperLink_TXPMCLK GND HyperLink_TXP1 HyperLink_TXN1 GND www.casql.com
IISC-6678 Board Hardware Design Manual May. 8th 2014
A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 HyperLink_RXP3 HyperLink_RXN3 GND HyperLink_RXPMDAT HyperLink_TXFLDAT GND HyperLink_RXP0 HyperLink_RXN0 GND HyperLink_RXP2 HyperLink_RXN2 GND C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 HyperLink_TXP3 HyperLink_TXN3 GND HyperLink_RXPMCLK HyperLink_RXFLDAT GND HyperLink_TXP0 HyperLink_TXN0 GND HyperLink_TXP2 HyperLink_TXN2 GND
Figure 3.5 The HyperLink Connector
3.2.4 T1、T2, Ethernet Connector
T1、T2are Gigabit RJ45 Ethernet connectors with integrated magnetic. They are driven by Marvell Gigabit Ethernet transceiver 88E1111. The connections are shown in the table below:
Table 3.6 Ethernet Connector pin out Pin 1(COM) 2(T1+) 3(T1+) 4(T1+) 5(T1+) 6(T1+) 7(T1+) 8(T1+) 9(T1+) 10(GND) 11(LEDG+) 12(LEDG_) 13(LEDY-) Signal Name 2.5V PHY_MDI0_P PHY_MDI0_N PHY_MDI1_P PHY_MDI2_P PHY_MDI2_N PHY_MDI1_N PHY_MDI3_P PHY_MDI3_N AGND_EARTH 2.5V PHY_LED_RX PHY_LED_LINK1000 www.casql.com
IISC-6678 Board Hardware Design Manual May. 8th 2014
14(LEDY+) 15(GND) 16(GND) 17(NC) 18(NC) 2.5V AGND_EARTH AGND_EARTH NC NC 3.2.5 TAP_FPGA1, FPGA JTAG Connector (For Factory Use Only)
TAP_FPGA1 is a 6-pin JTAG connector for the FPGA programming and the PHY boundary test of the factory only. The pin out for the connector is shown in the figure below:
Table 3.7 FPGA JTAG Connector pin out Pin Signal Name 1 VCC3V3_FPGA 2 GND 3 FPGA_TCK 4 FPGA_TDO 5 FPGA_TDI 6 FPGA_TMS 3.2.6 J3, FMC (FPGA Mezzanine Card) Connector
Two versions of the electro-mechanically compatible connector can be used on
commercial grade and conduction cooled form factors. The high-pin count connector has 400 contacts arranged in a 10x40 array. The low-pin count connector has 160 contacts and consists of two 2x40 rows of contacts within the 10x40 connector shell.
Figure 3.6 HPC-Female FMC Connector
Figure 3.7 HPC-Male FMC Connector
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IISC-6678 Board Hardware Design Manual May. 8th 2014
Figure 3.8 LPC-Female FMC Connector
Figure 3.9 LPC-Male FMC Connector
Table 3.8 LPC-FMC (FPGA Mezzanine Card) Connector pin out Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 Pin Name GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND Signal Name GND FMC_SSPCK DSPA_SSPCS1 GND GND DSPA_SSPMOSI DSPA_SSPMISO GND GND FMC_GPIO_P5 FMC_GPIO_N5 GND GND FMC_GPIO_P6 FMC_GPIO_N6 GND GND FMC_GPIO_P8 FMC_GPIO_N8 GND GND FMC_GPIO_P10 FMC_GPIO_N10 GND GND FMC_CLKA_125M_P FMC_CLKA_125M_N GND www.casql.com
IISC-6678 Board Hardware Design Manual May. 8th 2014
C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND Pin Name PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK GND FMC_CLKD_156M25_P FMC_CLKD_156M25_N GND GND NC 5V GND 5V GND 3V3 GND Signal Name NC GND GND DSPA_SRIOSGMIICLKP_C DSPA_SRIOSGMIICLKN_C GND GND FMC_GPIO_P4 FMC_GPIO_N4 GND FMC_GPIO_P2 FMC_GPIO_N2 GND FMC_GPIO_P3 FMC_GPIO_N3 GND FMC_GPIO_P7 FMC_GPIO_N7 GND FMC_GPIO_P9 FMC_GPIO_N9 GND FMC_GPIO_P12 FMC_GPIO_N12 GND FMC_GPIO_P18 FMC_GPIO_N18 GND PRSNTn www.casql.com
IISC-6678 Board Hardware Design Manual May. 8th 2014
D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 Pin G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V Pin Name GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_P GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P PWRENn PERSTn NC NC NC NC 3V3 GND 3V3 GND 3V3 Signal Name GND FMC_GPIO_P0 FMC_GPIO_N0 GND GND DSPA_SRIO_TXP3 DSPA_SRIO_TXN3 GND DSPA_SRIO_TXP0 DSPA_SRIO_TXN0 GND DSPA_SRIO_TXP1 DSPA_SRIO_TXN1 GND DSPA_SRIO_RXP0 DSPA_SRIO_RXN0 GND DSPA_PCIe_RX1P DSPA_PCIe_RX1N GND DSPA_PCIe_RX2P DSPA_PCIe_RX2N GND DSPA_SRIO_RXP2 DSPA_SRIO_RXN2 GND DSPA_SRIO_RXP3 DSPA_SRIO_RXN3 GND FMC_GPIO_P14 www.casql.com
IISC-6678 Board Hardware Design Manual May. 8th 2014
G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 Pin H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND Pin Name VREF_A_M2C PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P FMC_GPIO_N14 GND FMC_GPIO_P16 FMC_GPIO_N16 GND FMC_GPIO_P20 FMC_GPIO_N20 GND 1.8V GND Signal Name NC NC GND FMC_GPIO_P1 FMC_GPIO_N1 GND DSPA_PCIe_TX1P DSPA_PCIe_TX1N GND DSPA_PCIe_TX2P DSPA_PCIe_TX2N GND DSPA_SRIO_TXP2 DSPA_SRIO_TXN2 GND DSPA_SRIO_RXP1 DSPA_SRIO_RXN1 GND PCIE_CLK_REF+ PCIE_CLK_REF- GND FMC_GPIO_P11 FMC_GPIO_N11 GND FMC_GPIO_P13 FMC_GPIO_N13 GND FMC_GPIO_P17 FMC_GPIO_N17 GND FMC_GPIO_P15 www.casql.com
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H32 LA28_N FMC_GPIO_N15 H33 GND GND H34 LA30_P FMC_GPIO_P19 H35 LA30_N FMC_GPIO_N19 H36 GND GND H37 LA32_P FMC_GPIO_P21 H38 LA32_N FMC_GPIO_N21 H39 GND GND H40 VADJ 2.5V LA[00: 33]_P, LA[00:33]_N – User defined signals on Bank A located on the LPC CLK0_M2C_P, CLK0_M2C_N – A differential pair that is assigned for a clock signal, which is driven from the IO Mezzanine Module to the carrier card.
CLK1_M2C_P, CLK1_M2C_N – A differential pair that is assigned for a clock signal, which is driven from the IO Mezzanine Module to the carrier card.
GBTCLK0_M2C_P,GBTCLK0_M2C_ N–A differential pair shall be used as a reference clock for the DP data signals.
DP0_M2C_P, DP0_M2C_N, DP0_C2M_P, DP0_C2M_N - These signals form one multi-gigabit transceiver data pairs.
GA[0:1] - These signals provide geographical addressed of the module and are used for I2C channel select.
TRST_L - JTAG Reset. This signal provides asynchronous initialization of the TAP controller on the IO Mezzanine module.
TCK-JTAG Clock. This signal provides an independent clock reference for TAP controller operation.
TMS - JTAG Mode Select. This signal shall provide state control of the TAP controller on the IO Mezzanine module.
TDI - JTAG Data In. This signal provides for serial writes of test data and instructions into the IO Mezzanine module.
TDO - JTAG Data Out. This signal provides for serial writes of test data and instructions out of the IO Mezzanine module.
PRSNT_M2C_L - Module present signal. This signal allows the carrier to determine whether an IO Mezzanine module is present.
PG_C2M – Power Good Carrier Card. This signal asserts high by the carrier card when power supplies, VADJ, 12P0V, 3P3V, are within tolerance.
SCL – System Management I2C serial clock. This signal provides a clock reference to the IO Mezzanine module from the carrier card for a two-wire serial management bus. SDA - System Management I2C serial data. This signal provides a data line for a two-wire serial management bus.
VADJ – These pins carry an adjustable voltage level power from the carrier to the IO Mezzanine module.
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3.3 DIP and Pushbutton Switches
The IISC-6678 Board has 3 push button switches and five sliding actuator DIP switches. The RST_FULL1, RST_COLD1, and RST_WARM1 are push button switches while SW2, SW3, SW4, SW5 and SW6 are DIP switches. The function of each of the switches is listed in the table below:
Table 3.9 IISC-6678 Board Switches Switch RST_FULL1 RST_COLD1 RST_WARM1Warm Reset Event SW2 SW3 SW4 SW5 SW6 Function Full Reset Event Cold Reset Event (RFU) Warm Reset Event DSP Boot mode, DSP Configuration DSP boot Configuration DSP boot Configuration DSP boot Configuration, PLL setting, PCIe mode Selection PCIe Enable/Disable, User Switch 3.3.1 RST_FULL1, Full Reset
Pressing the RST_FULL1 button switch will issue a RESETFULL# signal to TMS320C6678 by the FPGA. It‟ll reset DSP and other peripherals.
3.3.2 RST_COLD1, Cold Reset
The button is reserved for future use.
3.3.3 RST_WARM1, Warm Reset
Pressing the RST_WARM1 button switch will issue a RESET# signal to TMS320C6678 by the FPGA.
The FPGA will assert the RESET# signal to the DSP and the DSP will execute either a HARD or SOFT reset by the configuration in the RSCFG register in PLLCTL.
3.3.4 SW2, SW3, SW4 and SW5, DSP boot mode and Configuration
SW2, SW3, SW4and SW5 are 4-position DIP switches, which are used for DSP ENDIAN, Boot Device, Boot Configuration, and PCI Express subsystem configuration.
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SW5 SW4 SW3 SW2
Figure 3.10 SW2, SW3, SW4 and SW5 default settings
Table 3.10 SW2, SW3, SW4and SW5, DSP Configuration Switch Boot Mode IBL NOR boot on image0(default) IBL NOR boot on image1 IBL NAND boot on image0 IBL NAND boot on image1 IBL TFTP boot I2C POST boot ROM SPI boot ROM SRIO boot ROM Ethernet boot ROM PCIe boot No boot DIP SW2 DIP SW3 DIP SW4 DIP SW5 Pin(1,2.3,4) Pin(1,2.3,4) Pin(1,2.3,4) Pin(1,2.3,4) (off,off,on,off) (on,on,on,on) (on,on,on,off) (on,on,on,on) (off,off,on,off) (off,off,on,off) (off,off,on,off) (off,off,on,off) (off,on,off,off) (off,off,on,on) (off,on,off,on) (off,on,on,off) (off,on,on,on) (off,on,on,on) (on,off,on,on) (off,off,on,on) (on,on,off,on) (on,on,on,on) (on,on,on,off) (on,on,on,off) (on,on,on,on) (on,on,on,on) (on,on,on,off) (on,on,on,off) (on,on,on,off) (on,on,on,off) (on,on,off,on) (on,off,on,off) (on,on,off,off) (on,on,on,off) (on,on,on,on) (on,on,on,on) (on,on,on,on) (on,on,on,on) (on,on,on,on) (on,on,on,on) (off,on,on,on) (off,on,on,on) (off,on,on,on) (off,on,on,on) (off,off,on,off) (on,on,on,on) (on,on,on,on) (on,on,on,on) 3.3.5 SW6, DSP PCIESS Enable and User Defined Switch Configuration
The first position is used for enabling the PCI Express Subsystem within the DSP. The second position is undefined by hardware and available for application software use. The following table describes the positions and corresponding functions on SW6
Table 3.11 SW6, DSP PCI Express Enable and User Switch错误！未找到引用源。3.4 System LEDs
The IISC-6678 Board has eight LEDs. Their positions on the board are indicated in figure 3.11. The description of each LED is listed in table below:
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Figure 3.11 IISC-6678 Board LEDs
Table 3.12 IISC-6678 Board LEDs LED Color Description D1~D4 Red TX and RX status of Ethernet D5 Yellow&Blue 5V and 3.3V are stable FPGA_D1 Yellow&Blue Debug LEDs FPGA_D2 Yellow&Blue Debug LEDs SYSPG_D1 Green All power rails are stable
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4. System Power Requirements
This chapter describes the power design of the IISC-6678 Board. It contains: 4.1 Power Requirements
4.2 Power Supply Distribution 4.3 Power Supply Boot Sequence
4.1 Power Requirements
Note that the power estimates stated in this section are maximum limits used in the design of the IISC-6678 Board. They have margin added to allow the IISC-6678 Board to support early silicon samples that normally have higher power consumption than eventual production units.
The maximum IISC-6678 Board power requirements are estimated to be: FPGA – 0.65W;
DSP Cooling Fans – 1.2W (+5Vdc/0.24A); Clock Generators & clock sources – 3.30W; DSP – 14.90W; [Worse Case] Core supplies: 13.0W;
Peripheral supplies: 1.90W;
DDR3 – 2.63W; 5 SDRAMs to support 64-bit with ECC of the DSP Misc – 0.33W;
SGMII PHY – 1.14W;
Table 4.1 IISC-6678 Board Voltage Table Device Input Net Name +5V TMS320C6678 DSPA_CVDD VCC1V0 +1V8 VCC1V5 DDR3 Memory VCC1V5 VCC0V75 NAND Flash +1V8 NOR Flash(SPI) +1V8 ICS8543 +3V3CLK +2V5 88E1111 VCC1V2 VCC1V2 FPGA VCC3V3_FPGA VCC1V8 Voltage 5V 0.9V~1.1V 1.0V 1.8V 1.5V 1.5V 0.75V 1.8V 1.8V 3.3V 2.5V 1.2V 1.2V 3.3V 1.8V Description Power Input for IISC-6678 Board DSP Core Power DSP Fixed Core Power DSP I/O Power DSP DDR3 and SERDES Power DDR3 RAM Power DDR3 RAM Termination Power NAND Flash Power SPI NOR Flash Power Clock Gen Power PHY Analog and I/O Power PHY Core Power FPGA Core Power FPGA I/O Power for 3.3V bank FPGA I/O Power for 1.8V bank www.casql.com
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4.2 The Power Supply Distribution
A high-level block diagram of the power supplies is shown in Figure 4.1. It is also shown on the schematic.
Figure 4.1 All the power supply on IISC-6678 Board
Individual control for each (remaining) voltage regulator is provided to allow flexibility in how the power planes are sequenced (Refer to section 4.3 for specific details). The goal of all power supply designs is to support the ambient temperature range of 0°C to 45°C.
The TMS320C6678 core power is supplied using a dual digital controller coupled to a high performance FET driver IC. Additional DSP supply voltages are provided by discrete TI Swift power supplies. The TMS320C6678 supports a VID interface to enable Smart-Reflex® power supply control for its primary core logic supply. Refer to the TMS320C6678 Data Manual and other documentation for an explanation of the Smart-Reflex® control.
Figure 4.1 shows that the IISC-6678 Board power supplies are a combination of switching supplies and linear supplies. The linear supplies are used to save space for small loads. The switching supplies are implemented for larger loads.
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4.3 The Power Supply Boot Sequence
Figure 4.2 Initial Power on Sequence Timing Diagram
Table 4.2 IISC-6678Board Sequence Timing Descriptions Step Power rails 1 2 3 4 5 6 7 Timing Description When the 5V power is supplied +3V3 Auto to the IISC-6678 Board, the 3.3V supply will turn on. Turn on 2.5V、 1.8Vand1.2V, +2V5 after 3.3V stable for 10mS. +1V8 10mS FPGA outputs to the DSP will be VCC1V2 locked(held at ground). DSPA_CVDD (DSP AVS core Enable the CVDD,after 2V5 1V8 5mS power) VCC1V2 are stable for 5mS. VCC1V0 (DSP CVDD1 fixed core Turn on VCC1V0, after CVDD 5mS power) stable for 5mS. Turn on VCC1V8 after VCC1V0 VCC1V8 (DSP IO power) 5mS stable for 5mS. Turn on VCC1V5 afterVCC1V8 VCC1V5 (DSP DDR3 power) 5mS stable for 5mS. Turn on VCC0V75 after VCC0V75 5mS VCC1V5 stable for 5mS. www.casql.com
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5. IISC-6678 Board FPGA Function Description
This chapter contains, 5.1 FPGA overview
5.2 FPGA signals description 5.3 Sequence of operation 5.4 Reset definition
5.1 FPGA overview
The FPGA (Xilinx XC3S200AN) controls the IISC-6678 Board power sequencing, reset mechanism, DSP boot mode configuration and clock initialization. The FPGA also provides the SRIO and Reference Clock between the FMC connector and the DSP.
The FPGA also supports 4 user LEDs and 1 user switch through control registers. All the FPGA registers are accessible by the TMS320C6678 DSP. The key features of the IISC-6678 Board FPGA are: IISC-6678 Board Power Sequence Control IISC-6678 Board Reset Mechanism Control
IISC-6678 Board Clock Generator Initialization and Control
TMS320C6678 DSP SPI Interface for Accessing the FPGA Configurable
Registers
Provides Shadow Registers for TMS320C6678 DSP to Access the Clock
Generator Configurations Registers
Provides TMS320C6678 DSP Boot Mode Configuration switch settings Provides the SRIO and Reference Clock between FMC and DSP Provide Ethernet PHY Interrupt(RFU) and Reset Control Interface Provides support for Reset Buttons, User Switches and Debug LEDs
5.2 FPGA signals description
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. Throughout this manual, a „#‟ or „Z‟ will be used at the end of a signal name to indicate that the active or asserted state occurs when the signal is at a low voltage level.
The following notations are used to describe the signal and type.
I Input pin O Output pin I/O Bi-directional pin Differential Differential Pair pins PU Internal Pull-Up
Table 5.1 IISC-6678 Board FPGA Pin Description
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IO Type DSP Boot & Device configuration : Pin Name BM_GPIO[00:15] I Description DSP Boot Mode Strap Configurations: These switch inputs are used to drive the DSP boot mode configuration during the IISC-6678 Board power up period. DSP GPIO: In normal operation mode, these signals are not driven by the FPGA so that the DSP can use them as GPIO pins. During the IISC-6678 Board power-on or during the RESETFULLz asserted period, the FPGA will output the BM_GPIO switch values to the DSP on these pins so the DSP can latch the boot mode configuration. DSP Core Selection Bit: The default value is 0000b and Register bits define the state of these pins. DSPA_PACLKSEL: This pin is used for the DSP PASS clock selection setting. The logic of this signal is derived from the BM_GPIO [13:11] state or configured by the FPGA registers. Latch Enable for DSP Local Reset and NMI inputs: The default value is 1b and a register bit defines the state of this pin. DSP NMI.: The default value is 1b and unlocked a register bit defines the state of this pin. DSP Local Reset: The default value is 1b and a register bit defines the state of this pin. DSP HOUT DSP Boot Complete Indication DSP System Clock Output DSP Power-On Reset DSP Full Reset DSP Reset LVCMOS status signaling. SDA/SCL bidirectional serial data www.casql.com
DSPA_GPIO[00:15] I/O DSP RESET & Interrupts Control : DSPA_CORESEL[0:3] O DSPA_PACLKSEL O DSPA_LRESETNMIENZ O DSPA_NMIZ O DSPA_LRESETZ DSPA_HOUT DSPA_BOOTCOMPLETE DSPA_SYSCLKOUT DSP_PORZ DSP_RESETFULLZ DSP_RESETZ Clock Generation: CDCL6010_LOCK CDCL6010_SDA O I I I O O O I O IISC-6678 Board Hardware Design Manual May. 8th 2014
CDCL6010_SCL Power Sequences Control : DSPA_VCC0V75_EN O SDA/SCL serial clock 0.75V Voltage Power Supply Enable: DSPA_VCC0V75_EN is for 0.75V power plane control. 1.0V Voltage Power Supply Enable: VCC1V0_EN is for 1.0V power plane control. CVDD Voltage Power Supply Enable: CVDD_EN is for CVDD power plane control. 1.5V Voltage Power Supply Enable: VCC1V5_EN is for 1.5V power plane control. 1.8V Voltage Power Supply Enable: VCC1V8_EN is for 1.8V power plane control. 1.5V Voltage Power Good Indication: This signal indicates the 1.5V power is valid. 1.0V Voltage Power Good Indication: This signal indicates the 1.0V power is valid. CVDD Voltage Power Good Indication: This signal indicates the CVDD power is valid. System Power Good Indication: This signal is indicated by the FPGA to the system when all the power supplies are valid. Full Reset Button Input: This button input is used to initiate a Full Reset event. Warm Reset Button Input: This button input is used to initiate a Warm Reset event. Cold Reset Button Input: Reserved for Future Use (RFU). Reset Request from the DSP Emulator Header: A warm Reset sequence will be initiated if an active TRGRSTZ event is recognized by the FPGA. O VCC1V0_EN O CVDD_EN O VCC1V5_INH O VCC1V8_EN O VCC1V5_PGOOD I VCC1V0_PGOOD I CVDD_PGOOD I SYS_PGOOD RESET Buttons and Requests : FULL_RESET WARM_RESET COLD_RESET (RFU) I I I I TRGRSTZ DEBUG LED: I www.casql.com
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DEBUG_LED[0:3] FPGA Storage (RFU): FPGA_SPI_CS# FPGA_SPI_SI FPGA_SPI_SCK FPGA_SPI_SO DSP SPI : O Debug LED: The LEDs are used for debugging purposes only. It can be configured by the registers in the FPGA. FPGA SPI Chip Select : (RFU) FPGA SPI Serial Data MOSI : (RFU) FPGA SPI Clock Output : (RFU) FPGA SPI Serial Data MISO : (RFU) DSP SPI Serial Data MISO: This signal is connected to the TMS320C6678 DSP SPIDIN pin. This signal is used for serial data transfers from the slave (FPGA) output to the master (DSP) input in the DSP_SSPCS1 asserted period. DSP SPI Chip Select 1: This signal is connected to the TMS320C6678 DSP SPISCS1 pin. The falling edge of the SSPCS1 from the DSP will initiate a transfer. If SSPCS1 is high, no data transfer can take place. DSP SPI Serial Data MOSI: This signal is connected to the DSP SPIDOUT pin. This signal is used for serial data transfers from the master (DSP) output to the slave (FPGA) input. DSP SPI Serial Clock: The FPGASPI bus clocks data in on the falling edge of SSPCK. Data transitions therefore occur on the rising edge of the clock. Interrupt Request from 88E111 PHY (RFU) Reset to 88E1111 PHY: This signal is used to reset the 88E1111 PHY device. The PHY_RST# will be asserted during the active DSP_PORZ or DSP_RESETFULLZ period. The PHY_RST# logic also can be configured by the DSP accessed register. O O O I DSPA_SSPMISO O DSPA_SSPCS1 I DSPA_SSPMOSI I FPGA_SSPCK PHY Interface : PHY_INT# I I PHY_RST# O FMC GPIO FMC_GPIO_P/N[0:21] O, Diff User defined differential signals FPGA JTAG TAP Control Port: www.casql.com
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FPGA_TCK FPGA_TDO FPGA_TDI FPGA_TMS Miscellaneous: MAIN_48MHZ_CLK_R I O I I FPGA JTAG Clock Input FPGA JTAG Data Output FPGA JTAG Data Input FPGA JTAG Mode Select Input FPGA Main Clock Source: A 48 MHz clock is used as the FPGA main clock source. DSP Timer 0 Clock: The FPGA provides a 24MHz clock to the DSP timer 0 input. During the IISC-6678 Board Power-on or RESETFULLZ asserted period, the FPGA will drive the PCIESSEN switch state to DSP for latching. NAND Flash Write Protect: This signal is used to control the NAND flash write-protect function. NOR Flash Write Protect: This signal is used to control the NOR flash write-protect function. EEPROM Write Protect: This signal is used to control the EEPROM write-protect function. PCIE Subsystem Enable: This is used for the PCIESSEN switch input. User Defined Switch: This is reserved for the user defined switch input. Extend IO I DSPA_TIMI0 O NAND_WP# O NOR_WP# O EEPROM_WP PCIESSEN USER_Define[0:2] FPGA_IO[1:6] FPGA Mode : FPGA_M[0:2] FPGA_VS[0:2] O I I I/O I FPGA_DONE Mode Select. Selects the FPGA configuration mode. Variant Select. Instructs the FPGA how to I communicate with the attached SPI Flash PROM. FPGA Configuration Done. Low during I/O configuration. Goes High when FPGA successfully completes configuration. Program FPGA. Active Low. When asserted low for 500 ns or longer, forces the FPGA to restart its configuration I process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. www.casql.com
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5.3 Sequence of operation
This section describes the FPGA sequence of operation on the IISC-6678 Board. It contains:
5.3.1 Power on Sequence 5.3.2 Power off Sequence
5.3.1 Power on Sequence
The following section provides details of the FPGA Power-On sequence of operation. After the IISC-6678 Board+3.3V voltage is valid and stable, and the FPGA
design code is loaded, the FPGA is ready for the Power-On sequence of operation.
The FPGA starts to execute the Power-On sequence. Wait for 10 ms, the FPGA
enable the 2.5V power.
Once the 2.5V voltage is valid, wait for 5 ms, the FPGA asserts the CVDD_EN
and VCC1V0_EN to enable the DSPA_CVDD and VCC1V0 DSP core power. After both the VCC1V0_PGOODand CVDD_PGOOD are all valid, wait for 5 ms,
the FPGA enables the 1.8V power.
After the 1.8V voltage is valid (VCC1V8_PGOOD asserted), wait for 5 ms and
then the FPGA enables the 1.5V power rail.
After the 1.5V voltage is valid (VCC1V5_PGOOD), wait for 5 ms, the FPGA
enables the 0.75V power and Level shift component output and initialize the LP2998.
After the 0.75V voltage is valid (VCC0V75_PGOOD asserted), waits for 5ms
and checks the CDCL6010_LOCK states, after the PLL states of the CDCL6010 are valid, the FPGA de-asserts the DSP_RESETz and DSPA_LRESETz and Keep the DSP_PORz and DSP_RESETFULLz in assertion.
After the DSP_RESETz and DSPA_LRESETz have de-asserted, wait for 5 ms,
the FPGA de-asserts the DSP_PORz and keeps the DSP_RESETFULLz still being asserted. Wait for another 5 ms, the FPGA de-asserts the DSP_RESETFULLz. The FPGA will drive the BM_GPIO switches value to the DSP for the DSP boot mode configuration strapping during the period from the VCC0P75_PGOOD is valid to the RESETSTAT# being de-asserted. The FPGA will also drive the PCIESSEN switch value to DSP_TIMI0 for the DSP boot configuration strapping.
Wait for the RESETSTAT# signal from DSP to go from low to high. The
IISC-6678 Board Power-On sequence is completed.
5.3.2 Power off Sequence
Following section provides details of FPGA power off sequence of operation.
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Once the system powers on, any power failure events (any one of power good
signals de-asserted) will trigger the FPGA to proceed to the power off sequence. Once any de-asserted Power Good signals have been detected by the FPGA, the
FPGA will assert the DSP_PORz and DSP_RESETFULLz to DSP immediately. Wait for 5 ms, the FPGA will disable all the system power rails by the enable pins
and clock generator by the power down pins, assert all the other DSP resets to DSP, lock the +1.8V output pins from the FPGA to the DSP.
FPGA remains in the power failure state until main 5V power is removed and
restored.
5.4 Reset definition
5.4.1 Reset Behavior
Power On: The Power On behavior includes initiating and sequencing the power
sources, clock sources and then DSP startup.
Full Reset: The RESETFULLz is asserted low to the DSP. This causes
RESETSTAT# to go low which triggers the boot configuration to be driven from the FPGA. Reset to the Marvell PHY is also asserted. POR# and RESET# to the DSP remain high. The power supplies and clocks operate without interruption.
Warm Reset: The RESETz is asserted low to the DSP. The PORz and
RESETFULLz to the DSP remain high. The power supplies and clocks operate without interruption.
5.4.2 Reset Switches and Triggers
(1) FULL_RESET (RST_FULL1) – a logic low state with a low to high transition will trigger a Full Reset behavior event.
When the push button switch RST_FULL1 is pressed, FPGA on IISC-6678 Board will assert DSP‟s RESETFULL# input to issue a total reset of the DSP, everything on the DSP will be reset to its default state in response to this event, boot configurations will be latched and the ROM boot process will be initiated.
This is equivalent to a power cycle of the board but POR and will have following effects:
Reset DSP
Reset Gigabit Ethernet PHY Reload boot parameters.
Protect the contents in the I2C EEPROM, NAND flash and SPI NOR flash.
(2) WARM_RESET (RST_WARM1) – a logic low state with a low to high transition will trigger a warm reset behavior event.
When the push button Switch RST_WARM1 is pressed, FPGA will assert a DSP
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RESET# input, which will reset the DSP. Software can program this to be either hard or soft. Hard reset is the default which resets almost everything. Soft Reset will behave like Hard Reset except that PCIe MMRs, EMIF16 MMRs, DDR3 EMIF MMRs, and External Memory contents are retained.
Boot configurations are not latched by Warm Reset. Also, Warm Reset will not reset blocks supporting Reset Isolation when they are appropriately configured previously by application software. Warm Reset must be used to wake from low-power sleep and hibernation modes.
In the case of a Soft Reset, the clock logic or the power control logic of the peripherals is not affected, and, therefore, the enabled/disabled state of the peripherals is not affected.
The following external memory contents are maintained During a Soft Reset:
DDR3 MMRs: The DDR3 Memory Controller registers are not reset. In addition,
the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.
PCIe MMRs: The contents of the memory connected to the EMIFA are retained.
The EMIFA registers are not reset.
(3) COLD_RESET (RST_COLD1) – not used in current implementation.
(4) TRGRSTz - a logic low state with a low to high transition on the Target Reset signal from emulation header that will trigger a warm reset behavior event.
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