SHARC®Embedded ProcessorADSP-21266SUMMARY
High performance 32-bit/40-bit floating-point processor optimized for high performance audio processingCode compatibility—at assembly level, uses the same instruction set as other SHARC DSPs
The ADSP-21266 processes high performance audio while enabling low system costs
Audio decoders and post processor algorithms support:
Nonvolatile memory can be configured to contain a combi-nation of PCM 96 kHz, Dolby® Digital, Dolby Digital Surround EXTM, DTS-ESTM Discrete 6.1, DTS-ES Matrix 6.1, DTS® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6TMVarious multichannel surround-sound decoders are con-tained in ROM. For configurations of decoder algorithms, see Table2 on Page6.
Single-instruction multiple-data (SIMD) computational archi-tecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register fileHigh bandwidth I/O—a parallel port, an SPI® port, six serial ports, a digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisi-tion port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU) On-chip memory—2M bits of on-chip SRAM and a dedicated 4M bits of on-chip mask-programmable ROM
The ADSP-21266 is available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page44.
COREPROCESSORINSTRUCTIONCACHE32؋48-BITDUALPORTEDMEMORYBLOCK0SRAM1MBITROM2MBITDUALPORTEDMEMORYBLOCK1SRAM1MBITROM2MBITTIMERDAG18؋4؋32DAG28؋4؋32PROGRAMSEQUENCERADDRDATAADDRDATA32PMADDRESSBUSDMADDRESSBUS6464PMDATABUSDMDATABUSDMACONTROLLER22CHANNELS32IOD(32)IOA(18)4PXREGISTERPROCESSINGELEMENT(PEX)PROCESSINGELEMENT(PEY)4GPIOFLAGS/IRQ/TIMEXPSPIPORT(1)ADDRESS/DATABUS/GPIO1636JTAGTEST&EMULATION20SIGNALROUTINGUNITSERIALPORTS(6)INPUTDATAPORTS(8)PARALLELDATAACQUISITIONPORTPRECISIONCLOCKGENERATORS(2)3TIMERS(3)IOPREGISTERS(MEMORYMAPPED)CONTROL,STATUS,DATABUFFERSCONTROL/GPIOPARALLELPORTSDIGITALAUDIOINTERFACEI/OPROCESSORFigure 1.Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use.Specifications subject to change without notice. No license is granted by implicationor otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective owners.
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ADSP-21266
KEY FEATURES
Serial ports offer left-justified sample-pair and I2S support via 12 programmable and simultaneous receive or trans-mit pins, which support up to 24 transmit or 24 receive I2S channels of audio when all 6 serial ports (SPORTs) are enabled or six full duplex TDM streams of up to 128 channels per frame
At 200 MHz (5 ns) core instruction rate, the ADSP-21266 operates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed- or floating-point data
400 MMACS sustained performance at 200 MHz
Super Harvard Architecture—three independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O
2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit block 1) for simultaneous access by core processor and DMA
4M bits on-chip dual-ported mask-programmable ROM (2M bits in block 0 and 2M bits in block 1)
Dual data address generators (DAGs) with modulo and bit-reverse addressing
Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing
Single instruction multiple data (SIMD) architecture provides:
Two computational processing elements
Concurrent execution—each processing element executes the same instruction, but operates on different data Parallelism in buses and computational units allows single cycle executions (with or without SIMD) of a multiply operation; an ALU operation; a dual memory read or write; and an instruction fetch
Transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle, sustained
2.4G byte/s bandwidth at 200 MHz core instruction rateIn addition, 900M byte/sec is available via DMA
Accelerated FFT butterfly computation through a multiply with add and subtract instructionDMA controller supports:
22 zero-overhead DMA channels for transfers between the ADSP-21266 internal memory and serial ports (12), the input data port (IDP) (eight), the SPI-compatible port (one), and the parallel port (one)
32-bit background DMA transfers at core clock speed, in parallel with full-speed processor execution
JTAG background telemetry for enhanced emulation features
IEEE 1149.1 JTAG standard test access port and on-chip emulation
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packagesAlso available in lead-free packages
Digital audio interface includes six serial ports, two precision clock generators, an input data port, three programmable timers, and a signal routing unit
Asynchronous parallel/external port provides:Access to asynchronous external memory
16 multiplexed address/data lines that can support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data66M byte/sec transfer rate for 200 MHz core rate50M byte/sec transfer rate for 150 MHz core rate256 word page boundaries
External memory access in a dedicated DMA channel8- to 32-bit and 16- to 32-bit word packing optionsProgrammable wait state options: 2 to 31 CCLKSerial ports provide:
Six dual data line serial ports that operate at up to
50M bits/sec for a 200 MHz core and up to 37.5M bits/sec for a 150 MHz core on each data line—each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair
Left-justified sample-pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S-compatible stereo devices per serial port
TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony inter-faces such as H.100/H.110
Up to 12 TDM stream support, each with 128 channels per frame
Companding selection on a per channel basis in TDM modeInput data port provides an additional input path to the SHARC core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port
Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode
Signal routing unit (SRU) provides configurable and flexible connections between all DAI components, six serial ports, two precision clock generators, three timers, an input data port/parallel data acquisition port, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px)Serial peripheral interface (SPI)
Master or slave serial boot through SPI Full-duplex operation
Master-slave mode multimaster supportOpen drain outputs
Programmable baud rates, clock polarities, and phases3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired lineROM-based security features:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit access under program control to sensitive codePLL has a wide variety of software and hardware multi-plier/divider ratios
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ADSP-21266
TABLE OF CONTENTSGeneral Description ................................................. 4ADSP-21266 Family Core Architecture ...................... 4ADSP-21266 Memory and I/O Interface Features ......... 6Target Board JTAG Emulator Connector .................... 9Development Tools ............................................... 9Evaluation Kit ..................................................... 10Designing an Emulator-Compatible
DSP Board(Target) ........................................... 10Additional Information ......................................... 10Pin Function Descriptions ........................................ 11Address Data Pins as Flags ..................................... 14Core Instruction Rate to CLKIN Ratio Modes ............. 14Address Data Modes ............................................. 14ADSP-21266 Specifications ....................................... 15Recommended Operating Conditions ....................... 15Electrical Characteristics ........................................ 15Absolute Maximum Ratings ................................... 16ESD Sensitivity .................................................... 16Timing Specifications ........................................... 17Output Drive Currents .......................................... 37Test Conditions ................................................... 37Capacitive Loading ............................................... 37Environmental Conditions ..................................... 38Thermal Characteristics ........................................ 38136-Ball BGA Pin Configurations ............................... 39144-Lead LQFP Pin Configurations ............................. 42Package Dimensions ................................................ 43Ordering Guide ...................................................... 44
REVISION HISTORY
5/05—Rev. A to Rev. B
Miscellaneous Format Updates..........................UniversalChanged “Digital Applications Interface” to
“Digital Audio Interface”.....................................GlobalApplied corrections and additional information to:
Summary ............................................................ 1ADSP-21266 Benchmarks (at 200 MHz) ..................... 4Dual-Ported On-Chip Memory ................................ 6Power Supplies ..................................................... 8Analog Power Filter Circuit ..................................... 9Pin Descriptions ................................................. 11Recommended Operating Conditions ...................... 15JTAG Test Access Port and Emulation ..................... 36Output Drive Currents ......................................... 37Capacitive Loading .............................................. 37Environmental Conditions .................................... 38Thermal Characteristics ........................................ 38136-Ball BGA Pin Assignments ............................... 39144-Lead LQFP Pin Assignments ............................ 42Package Dimensions ............................................ 43Ordering Guide .................................................. 44
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ADSP-21266
GENERAL DESCRIPTIONThe ADSP-21266 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Har-vard Architecture. The ADSP-21266 is source code compatible with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. Like other SHARC DSPs, the ADSP-21266 is a 32-bit/40-bit floating-point proces-sor optimized for high performance audio applications with its dual-ported on-chip SRAM, mask-programmable ROM, multi-ple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface.
As shown in the Functional Block Diagram on Page 1, the ADSP-21266 uses two computational units to deliver a 5 to 10 times performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21266 DSP achieves an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at 150 MHz. With its SIMD computational hardware, the ADSP-21266 can perform 1200 MFLOPS running at 200 MHz, or 900 MFLOPS running at 150 MHz.
Table1 shows performance benchmarks for the ADSP-21266.Table 1.ADSP-21266 Benchmarks (at 200 MHz)
Speed
Benchmark Algorithm(at 200 MHz)1024 Point Complex FFT (Radix 4, with reversal)61.3 µsFIR Filter (per tap)13.3 ns
13.3 ns IIR Filter (per biquad)1Matrix Multiply (pipelined)[3×3] × [3×1]30 ns[4×4] × [4×1]53.3 nsDivide (y/×)20 ns Inverse Square Root30 ns
1•Three programmable interval timers with PWM genera-tion, PWM capture/pulse width measurement, and
external event counter capabilities•On-chip dual-ported SRAM (2M bit)
•On-chip dual-ported, mask-programmable ROM (4M bit)
•JTAG test access port
•8- or 16-bit parallel port that supports interfaces to off-chip memory peripherals•DMA controller
•Six full-duplex serial ports•SPI-compatible interface
•Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), six serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three programmable timers, and a flexible signal routing unit (SRU)
Figure2 shows one sample configuration of a SPORT using the precision clock generator to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible.
ADSP-21266 FAMILY CORE ARCHITECTURE
The ADSP-21266 is code compatible at the assembly level with the ADSP-2136x and ADSP-2116x, and with the first generation ADSP-2106x SHARC DSPs. The ADSP-21266 shares architec-tural features with the ADSP-2136x and ADSP-2116x SIMD SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21266 contains two computational processing ele-ments that operate as a single-instruction multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing ele-ments, but each processing element operates on different data. This architecture is efficient at executing math intensive audio algorithms.
Entering SIMD mode also has an effect on the way data is trans-ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band-width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.
Assumes two files in multichannel SIMD mode.
The ADSP-21266 continues SHARC’s industry-leading stan-dards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include 2M bit dual-ported SRAM memory, 4M bit dual-ported ROM, an I/O processor that supports 22 DMA channels, six serial ports, an SPI interface, external parallel bus, and digital audio interface.
The block diagram of the ADSP-21266 onPage1 illustrates the following architectural features:
•Two processing elements, each containing an ALU, multi-plier, shifter, and data register file•Data address generators (DAG1, DAG2)•Program sequencer with instruction cache
•PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core pro-cessor cycle
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ADSP-21266
ADSP-21266CLOCK223CLKINXTALCLK_CFG1–0BOOTCFG1–0FLAG3–1RDWRFLAG0ADC(OPTIONAL)CLKFSSDATCONTROLDATACLKOUTALEAD15–0LATCHADDRDATAOEWECSADDRESSPARALLELPORTRAM,ROMBOOTROMI/ODEVICEDAI_P1DAI_P2DAI_P3SRUDAI_P18DAI_P19DAI_P20SCLK0SFS0SD0ASD0BSPORT0SPORT1SPORT2SPORT3SPORT4SPORT5DAC(OPTIONAL)CLKFSSDATCLKFSDAIRESETPCGAPCGBJTAG6Figure 2.ADSP-21266 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera-tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele-ments. These computation units support IEEE 32-bit single precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats.
Single-Cycle Fetch of Instruction and Four OperandsThe ADSP-21266 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro-gram memory (PM) bus transfers both instructions and data (see Figure1 on Page1). With the ADSP-21266’s separate pro-gram and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.
Instruction Cache
The ADSP-21266 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2126x enhanced Har-vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.
Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
The ADSP-21266’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program-ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and
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ADSP-21266
Fourier transforms. The two DAGs of the ADSP-21266 contain sufficient registers to allow the creation of up to 32 circular buff-ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-head, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.
ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point for-mats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the
ADSP-21266 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch-ing up to four 32-bit values from memory—all in a single instruction.
DMA Controller
The ADSP-21266’s on-chip DMA controller allows zero-over-head data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simul-taneously executing its program instructions. DMA transfers can occur between the ADSP-21266’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) port, the IDP (input data port), parallel data acquisition port (PDAP), or the parallel port. Twenty-two channels of DMA are available on the ADSP-21266—one for the SPI interface, 12 via the serial ports, eight via the input data port, and one via the processor’s parallel port. Programs can be downloaded to the ADSP-21266 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA trans-fers, and DMA chaining for automatic linked DMA transfers.
ADSP-21266 MEMORY AND I/O INTERFACE FEATURES
The ADSP-21266 adds the following architectural features to the SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21266 contains two megabits of internal SRAM and four megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see memory map, Figure3). Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor. The dual-ported memory, in com-bination with three separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a sin-gle cycle.
The ADSP-21266 is available with a variety of multichannel surround-sound decoders, preprogrammed in on-chip ROM memory. Table2 indicates the configurations of decoder algo-rithms provided.
Table 2.Multichannel Surround-Sound Decoder Algorithms in On-Chip ROM
AlgorithmsPCMAC-3
DTS 96/24AAC (LC)
B ROMYesYesv2.2Yes
C ROMYesYesv2.3Yes
D ROMYesYesv2.3Coef-ficients onlyYesNoYesYesYes
Digital Audio Interface (DAI)
The digital audio interface provides the ability to connect vari-ous peripherals to any of the SHARC’s DAI pins (DAI_P20–1). Connections are made using the signal routing unit (SRU, shown in the block diagram onPage1).
The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon-nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon-figurable signal paths.
The DAI also includes six serial ports, two precision clock gen-erators (PCGs), an input data port (IDP), six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-21266 core, configurable as either eight channels of I2S or serial data, or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21266’s serial ports.
For complete information on using the DAI, see the ADSP-2126x SHARC DSP Peripherals Manual.
WMAPRO 7.1 96 KHzMPEG2 BC 2chNoiseDPL2x/EX
Neo:6/ES (v2.5046)NoYesYesDPL2YesNoYesYesYesYes
The ADSP-21266’s SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of differ-ent word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
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ADSP-21266
ADDRESSIOPREGISTERS0x00000000–0x0003FFFF0x00040000BLOCK0SRAM(1MBIT)0x00043FFFRESERVED0x00044000–0x00057FFF0x00058000LONGWORDADDRESSSPACEBLOCK0ROM(2MBIT)0x0005FFFF0x00060000BLOCK1SRAM(1MBIT)0x00063FFFRESERVEDBLOCK1ROM(2MBIT)0x0007FFFF0x00080000BLOCK0SRAM(1MBIT)0x00087FFFRESERVED0x00088000–0x000AFFFF0x000B00000x000BFFFF0x000C0000BLOCK1SRAM(1MBIT)0x000C7FFFRESERVEDBLOCK1ROM(2MBIT)30x000C8000–0x000EFFFF0x000F00000x000FFFFF0x00100000BLOCK0SRAM(1MBIT)0x0010FFFFRESERVED0x00110000–0x0015FFFF0x00160000BLOCK0ROM(2MBIT)0x0017FFFF0x00180000BLOCK1SRAM(1MBIT)0x0018FFFF0x00190000–0x001DFFFF0x001E00000x001FFFFF0x02FFFFFF0x03000000RESERVED0x3FFFFFFFEXTERNALDMAADDRESSSPACE1,40x00064000–0x00077FFF0x00078000RESERVED0x002000000x00FFFFFF0x01000000ADDRESSNORMALWORDADDRESSSPACEBLOCK0ROM(2MBIT)2EXTERNALMEMORYSPACESHORTWORDADDRESSSPACE1EXTERNALMEMORYISNOTDIRECTLYACCESSIBLEBYTHECORE.DMAMUSTBEUSEDTOREADORWRITETOTHISMEMORYUSINGTHESPIORPARALLELPORT.2BLOCK0ROMHASA48-BITADDRESSRANGE(0x000A0000–0x000AAAAA).3BLOCK1ROMHASA48-BITADDRESSRANGE(0x000E0000–0x000EAAAA).4USETHEEXTERNALADDRESSESLISTEDHEREWITHTHEPARALLELPORTDMAREGISTERS.THEPARALLELPORTGENERATESADDRESSWITHINTHERANGE0x00000000–0x00FFFFFF.RESERVEDBLOCK1ROM(2MBIT)INTERNALMEMORYSPACEFigure 3.ADSP-21266 Memory Map
Serial Ports
The ADSP-21266 features six full duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the Analog Devices AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has its own dedicated DMA channel.Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTs are enabled, or six full duplex TDM streams of 128 channels per frame.
Rev. B
The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of 50M bits/sec for a 200 MHz core and 37.5M bits/sec for a
150MHz core. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit sig-nals while the other SPORT provides the two receive signals. The frame sync and clock are shared.Serial ports operate in four modes: •Standard DSP serial mode•Multichannel(TDM)mode
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ADSP-21266
•I2S mode
•Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var-ious attributes of this mode.
Each of the serial ports supports the left-justified sample-pair and I2S protocols (I2S is an industry-standard interface com-monly used by audio codecs, ADCs, and DACs), with two data pins, allowing four left-justified sample-pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 24 audio channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated.
Timers
The ADSP-21266 has a total of four timers: a core timer able to generate periodic software interrupts, and three general-pur-pose timers that can generate periodic interrupts and be independently set to operate in one of three modes:•Pulsewaveformgeneration mode•Pulsewidthcount/capture mode•External event watchdog mode
The core timer can be configured to use flag3 as a timer expired output signal, and each general-purpose timer has one bidirec-tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin-gle control and status register enables or disables all three general-purpose timers independently.
ROM-Based Security
The ADSP-21266 has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any exter-nal code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through
the JTAG or test access port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.
Serial Peripheral (Compatible) Interface
Serial peripheral interface is an industry-standard synchronous serial link, enabling the ADSP-21266 SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21266 SPI-compatible peripheral implementation also features programmable baud rates up to 37.5 MHz, clock phases, and polarities. The ADSP-21266 SPI-compatible port uses open drain drivers to support a multimas-ter configuration and to avoid data contention.
Program Booting
The internal memory of the ADSP-21266 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOTCFG1–0) pins. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16-bit, the maximum data transfer rate is one-third the core clock speed. As an example, a clock rate of 200 MHz, is equivalent to 66M byte/sec, and a clock rate of 150 MHz is equivalent to 50Mbyte/sec.
DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the paral-lel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port.
Phase-Locked Loop
The ADSP-21266 uses an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via soft-ware control. The ratios are made up of software configurable numerator values from 1 to 32 and software configurable divi-sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21266 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply.
Note that the analog supply pin (AVDD) powers the ADSP-21266’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit
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ADSP-21266
for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure4. (A recommended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure4 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip.
ADSP-212xxAVDDdevelopment environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21266.
The VisualDSP++ project management environment lets pro-grammers develop and debug an application. This environment includes an easy to use assembler (which is based on an alge-braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The ADSP-21266 SHARC DSP has architectural features that improve the efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa-tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in com-plexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Sta-tistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and effi-ciently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.
Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:
•View mixed C/C++ and assembly code (interleaved source and object information)•Insert breakpoints
•Set conditional breakpoints on registers, memory, andstacks
•Trace instruction execution
•Perform linear or statistical profiling of program execution•Fill, dump, and graphically plot the contents of memory•Perform source level debugging•Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC devel-opment tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:•Control how the development tools process inputs and generate outputs
•Maintain a one-to-one correspondence with the tools’ command line switches
‡100nFVDDINT10nF1nFHIZFERRITEBEADCHIPAVSSLOCATEALLCOMPONENTSCLOSETOAVDDANDAVSSPINSFigure 4.Analog Power Filter Circuit
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro-cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces-sor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro-priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
The ADSP-21266 is supported by a complete automotive refer-ence design and development board as well as by a complete home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and post processing algorithms that are factory programmed into the ROM space of the ADSP-21266. SIMD optimized libraries consume less processing resources, which results in more avail-able processing power for custom proprietary features.The nonvolatile memory of the ADSP-21266 can be configured to contain a combination of Dolby Digital, Dolby Pro Logic, Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24, and Neo:6. Multiple S/PDIF and analog I/Os are provided to maximize end system flexibility.
The ADSP-21266 is also supported with a complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and VisualDSP++®‡
†CROSSCORE is a registered trademark of Analog Devices, Inc.VisualDSP++ is a registered trademark of Analog Devices, Inc.
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The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the mem-ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the gen-eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.VisualDSP++ Component Software Engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applica-tions. It also is used for downloading components from the Web, dropping them into the application, and publishing com-ponent archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utiliza-tion in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, and examine run-time stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphi-cal and textual environments.
In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard-ware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram designtools.
are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the Visu-alDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit, without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any cus-tom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonin-trusive emulation.
DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD(TARGET)
The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG inter-face—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal fea-tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on sys-tem timing.
To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace withimprovements to emulator support.
EVALUATION KIT
Analog Devices offers a range of EZ-KIT Lite®† evaluation plat-forms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21266 architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference.
†EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
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PIN FUNCTION DESCRIPTIONSADSP-21266 pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-tified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following:
•DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI and AD15–0 (NOTE: These pins have internal pull-up resistors.)
The following symbols appear in the Type column of Table3: A = asynchronous, G = ground, I=input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state.
Table 3.Pin Descriptions
Pin TypeAD15–0I/O/T
State During and
After Reset
Rev. 0.1 silicon— AD15–0 pins are driven low both during and after reset.
Rev. 0.2 silicon— AD15–0 pins are three-stated and pulled high both during and after reset.
Function
Parallel Port Address/Data. The ADSP-21266 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address Data Modes on Page14 for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, A23–8; ALE is used in conjunction with an external latch to retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A15–0; ALE is used in conjunction with an external latch to retain the values of the A15–0. To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. See Table4 on Page14 for a list of how the AD15–0 pins map to the flag pins. When configured in the IDP_PDAP_CTL register, the IDP Channel 0 can use these pins for parallel input data.
Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or high116-bit data from an external memory device. When AD15–0 are flags, this pin
remains deasserted.
Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or high116-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted.
Output only, driven Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a low1new address on the parallel port address pin. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted.
Three-stateFlag Pins. Each FLAG pin is configured via control bits as either an input or output.
As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which indicates that the system timer has expired.
RDO
WRO
ALEO
FLAG3–0
I/O/A
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Table 3.Pin Descriptions (Continued)
Pin TypeDAI_P20–1I/O/T
State During and
After Reset
Three-state with programmable pull-up
Function
Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The config-uration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators, and timers to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode.
Serial Peripheral Interface Slave Device Select. An active low signal used to select the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the DSP’s SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21266 to ADSP-21266 SPI interaction, any of the master ADSP-21266’s flag pins can be used to drive the SPIDS signal on the ADSP-21266 SPI slave device.SPI Master Out Slave In. If the ADSP-21266 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21266 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21266 SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode.
SPI Master In Slave Out. If the ADSP6 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP6 is configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-mitting output data. In an ADSP6 SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the DSP’s MISO pin may be disabled by setting (=1) Bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins must be valid before reset is asserted. See Table5 on Page14 for a description of the boot modes.
SPICLKI/O
Three-state with pull-up enabled
SPIDSIInput only
MOSII/O (O/D)
Three-state with pull-up enabled
MISOI/O (O/D)
Three-state with pull-up enabled
BOOTCFG1–0
IInput only
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Table 3.Pin Descriptions (Continued)
Pin TypeCLKINI
State During and
After ResetInput only
Function
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input. It configures the ADSP-21266 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21266 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table6 for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-plier and divider in the PMCTL register at any time after the core comes out of reset.Reset Out/Local Clock Out. Drives out the core reset signal to an external device. CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL register. The default is reset out.
Processor Reset. Resets the ADSP-21266 to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21266.Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP6. TRST has a 22.5 kΩ internal pull-up resistor.
Emulation Status. Must be connected to the ADSP6 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal pull-up resistor.
Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor (13 pins on the BGA package, 32 pins on the LQFP package).
I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP package).
Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on Page8.Analog Power Supply Return.
Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
XTALCLKCFG1–0
OI
Output only2Input only
RSTOUT/CLKOUTOOutput only
RESETI/AInput only
TCKTMSTDITDOTRSTII/SI/SOI/A
Input only3Three-state with pull-up enabledThree-state with pull-up enabledThree-state4Three-state with pull-up enabledThree-state with pull-up enabled
EMUO (O/D)
VDDINTVDDEXTAVDDPPP
AVSSGND
12GG
RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.Output only is a three-state driver with its output path always enabled.3Input only is a three-state driver, with both output path and pull-up disabled.4Three-state is a three-state driver, with pull-up disabled.
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ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port.Table 4.AD15–0 to FLAG Pin Mapping
AD PinAD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15
Flag PinFLAG8FLAG9FLAG10FLAG11FLAG12FLAG13FLAG14FLAG15FLAG0FLAG1FLAG2FLAG3FLAG4FLAG5FLAG6FLAG7
ADDRESS DATA MODES
Table7 shows the functionality of the AD pins for 8-bit and
16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15–A0 when asserted, followed by data bits D15–D0 when deasserted.Table 7.Address/Data Mode Selection
EP Data Mode8-bit8-bit16-bit16-bit
ALEAssertedDeassertedAssertedDeasserted
AD7–0 FunctionA15–8D7–0A7–0D7–0
AD15–8 FunctionA23–16A7–0A15–8D15–8
Boot Modes
Table 5.Boot Mode Selection
BOOTCFG1–000011011
Booting ModeSPI Slave BootSPI Master Boot
Parallel Port Boot via EPROM
Internal Boot Mode (ROM code only)
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
Table 6.Core Instruction Rate/CLKIN Ratio Selection
CLKCFG1–000011011
CoretoCLKINRatio3:116:18:1
Reserved
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ADSP-21266 SPECIFICATIONSRECOMMENDED OPERATING CONDITIONS
Parameter1VDDINTAVDDVDDEXTVIH VIL VIH_CLKIN VIL_CLKIN TAMB K Grade
12Min
Internal (Core) Supply VoltageAnalog (PLL) Supply VoltageExternal (I/O) Supply Voltage
High Level Input Voltage2 @ VDDEXT = maxLow Level Input Voltage2 @ VDDEXT = minHigh Level Input Voltage3 @ VDDEXT = maxLow Level Input Voltage @ VDDEXT = minAmbient Operating Temperature4, 5
1.141.143.132.0–0.51.74–0.50
Max1.261.263.47+0.8+1.19+70
UnitVVVVV°C
VDDEXT + 0.5VVDDEXT + 0.5V
Specifications subject to change without notice.
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.3Applies to input pin CLKIN.4See Thermal Characteristics on Page38 for information on thermal specifications.5See Engineer-to-Engineer Note (No. 216) for further information.
ELECTRICAL CHARACTERISTICS
Parameter1VOHVOLIIHIILIILPUIOZHIOZLIOZLPUIDD-INTYPAIDDCIN12Test Conditions
High Level Output Voltage2Low Level Output Voltage2High Level Input Current4, 5Low Level Input Current4Low Level Input Current Pull-Up5Three-State Leakage Current 6, 7, 8Three-State Leakage Current6Three-State Leakage Current Pull-Up7Supply Current (Internal)9, 10, 11Supply Current (Analog)12Input Capacitance13, 14@ VDDEXT = min, IOH = –1.0 mA3@ VDDEXT = min, IOL = 1.0 mA3@ VDDEXT = max, VIN = VDDEXT max@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = VDDEXT max@ VDDEXT = max, VIN = 0 V@ VDDEXT = max, VIN = 0 V
tCCLK = 5.0 ns, VDDINT = 1.2 V, TAMB = +25°CAVDD = max
fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V
Min2.4
Max0.410102001010200500104.7
UnitVVµAµAµAµAµAµAmAmApF
Specifications subject to change without notice.
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.3See Output Drive Currents on Page37 for typical drive current capabilities.4Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.5Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.6Applies to three-statable pins: FLAG3–0.7Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, MISO, MOSI.8Applies to open-drain output pins: EMU, MISO, MOSI.9Typical internal current data reflects nominal operating conditions.10See Engineer-to-Engineer Note (No. 216) for further information.11Characterized, but not tested.12Characterized, but not tested.13Applies to all signal pins.14Guaranteed, but not tested.
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ABSOLUTE MAXIMUM RATINGS
ParameterRating
Internal (Core) Supply Voltage (VDDINT)1 –0.3 V to +1.4 VAnalog (PLL) Supply Voltage (AVDD)1 –0.3 V to +1.4 VExternal (I/O) Supply Voltage (VDDEXT)1–0.3 V to +3.8 V
VInput Voltage –0.5 V to VDDEXT1 +0.5 Output Voltage Swing –0.5 V to VDDEXT1 +0.5 VLoad Capacitance1200 pF
Storage Temperature Range1 –65°C to +150°CJunction Temperature under Bias125°C
1Stresses greater than those listed above may cause permanent damage to thedevice. These are stress ratings only; functional operation of the device at theseor any other conditions greater than those indicated in the operational sectionsof this specification is not implied. Exposure to absolute maximum rating condi-tions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21266 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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TIMING SPECIFICATIONS
The ADSP-21266’s internal clock (a multiple of CLKIN) pro-vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and exter-nal (CLKIN) clock frequency with the CLKCFG1–0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider con-trol of each port (DIVx for the serial ports).
The ADSP-21266’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This
I
PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control (Table8 and Table9).
Table 8.ADSP-21266 CLKOUT and CCLK Clock Generation Operation
Timing RequirementsDescriptionCalculationCLKN nput Clock1/tCK CCLKCore Clock1/tCCLKCLKOUTCLKINXTALXTALOSCPLLICLKPLL3:1,8:1,16:1CCLK(CORECLOCK)CLK-CFG[1:0]Figure 5.Core Clock and System Clock Relationship to CLKIN
Switching characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching char-acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
Table 9.Clock Periods
Timing
RequirementstCKtCCLKtSCLKtSPICLK1Description1CLKIN Clock Period
(Processor) Core Clock Period
Serial Port Clock Period = (tCCLK) × SRSPI Clock Period = (tCCLK) × SPIR
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register)
DAI_Px = serial port clockSPICLK = SPI clock
Figure5 shows core to CLKIN ratios of 3:1, 8:1, and 16:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP-2126x SHARC DSP Core Manual.
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times.See Figure30 on Page37 under Test Conditions for voltage reference levels.
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ADSP-21266
Power-Up Sequencing
The timing requirements for DSP startup are given in Table10 and Figure6.
Table 10.Power-Up Sequencing (DSP Startup)
ParameterTiming RequirementstRSTVDDtIVDDEVDDtCLKVDDtCLKRSTtPLLRSTRESET Low Before VDDINT/VDDEXT OnVDDINT On Before VDDEXTCLKIN Valid After VDDINT/VDDEXT Valid1CLKIN Valid Before RESET DeassertedPLL Control Setup Before RESET Deasserted0–500102203200200
nsmsmsµsµs
Min
Max
Unit
Switching CharacteristictCORERST1DSP Core Reset Deasserted After RESET Deasserted4096tCK 4, 5Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.2Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.3Based on CLKIN cycles.4Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins.5The 4096 cycle count depends on tSRST specification in Table12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.
RESETtRSTVDDVDDINTtIVDDEVDDVDDEXTtCLKVDDCLKINtCLKRSTCLK_CFG1–0tPLLRSTRSTOUT*tCORERST*MULTIPLEXEDWITHCLKOUTFigure 6.Power-Up Sequencing
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ADSP-21266
Clock Input
See Table11 and Figure7.Table 11.Clock Input
Parameter
Timing RequirementstCKCLKIN Period
CLKIN Width LowtCKLtCKHCLKIN Width HightCKRFCLKIN Rise/Fall (0.4 V – 2.0 V)tCCLKCCLK Period312150 MHz
Min2017.517.516.66
Max1602802802310
200 MHzMin1516161 5
Max1602802802310
Unitns ns ns nsns
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.3Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
tCKCLKINtCKHtCKLFigure 7.Clock Input
Clock Signals
The ADSP-21266 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21266 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure8 shows the component connections used for a crystal operating in fun-damental mode. Note that the 200 MHz clock rate is achieved using a 12.5 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN).
CLKIN1M⍀XTALC1X1C2NOTE:C1ANDC2ARESPECIFICTOCRYSTALSPECIFIEDFORX1.CONTACTCRYSTALMANUFACTURERFORDETAILS.CRYSTALSELECTIONMUSTCOMPLYWITHCLKCFG1-0=10OR=01.Figure 8.150 MHz or 200 MHz Operation with a 12.5 MHz
Fundamental Mode Crystal
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ADSP-21266
Reset
See Table12 and Figure9.Table 12.Reset
Parameter
Timing RequirementstWRSTRESET Pulse Width Low1tSRSTRESET Setup Before CLKIN Low1Min
4tCK8
Max
Unit nsns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than100µs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKINtWRSTRESETtSRSTFigure 9.Reset
Interrupts
The timing specification in Table13 and Figure10 applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins when configured as interrupts.Table 13.Interrupts
Parameter
Timing RequirementtIPW IRQx Pulse WidthDAI_P20–1(FLG2–0)(IRQ2–0)Min
2 × tCCLK +2
Max
Unit ns
tIPWFigure 10.Interrupts
Core Timer
The timing specification in Table14 and Figure11 applies to FLAG3 when it is configured as the core timer (CTIMER). Table 14.Core Timer
Parameter
Switching Characteristic
CTIMER Pulse WidthtWCTIMMin
4 × tCCLK – 1
Max
Unit ns
FLG3(CTIMER)tWCTIMFigure 11.Core Timer
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ADSP-21266
Timer PWM_OUT Cycle Timing
The timing specification in Table15 and Figure12 applies to Timer in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
Table 15.Timer PWM_OUT Timing
Parameter
Switching CharacteristictPWMOTimer Pulse Width Output
Min2 tCCLK – 1
Max2(231 – 1) tCCLKUnitns
tPWMODAI_P20–1(TIMER)Figure 12.Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The timing specification in Table16 and Figure13 applies to Timer in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
Table 16.Timer Width Capture Timing
Parameter
Timing RequirementtPWITimer Pulse Width
Min2 tCCLKMax2(231 – 1) tCCLKUnitns
tPWIDAI_P20–1(TIMER)Figure 13.Timer Width Capture Timing
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ADSP-21266
DAI Pin-to-Pin Direct Routing
See Table17 and Figure14for direct pin connections only (for example DAI_PB01_I to DAI_PB02_O).Table 17.DAI Pin-to-Pin Routing
Parameter
Timing RequirementtDPIODelay DAI Pin Input Valid to DAI Output Valid
Min1.5
Max10
Unitns
DAI_PnDAI_PmtDPIOFigure 14.DAI Pin-to-Pin Direct Routing
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ADSP-21266
Precision Clock Generator (Direct Pin Routing)
The timing in Table18 and Figure15 is valid only when the SRU is configured such that the precision clock generator
(PCG) takes its inputs directly from the DAI pins (via pin buff-ers) and sends its outputs directly to the DAI pins. For the other Table 18.Precision Clock Generator (Direct Pin Routing)
Parameter
Timing RequirementstPCGIWInput Clock Pulse WidthtSTRIGPCG Trigger Setup Before Falling Edge of PCG Input Clock
PCG Trigger Hold After Falling Edge of PCG Input ClocktHTRIGMin20
22
Max
Unitnsnsns
cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteris-tics apply to external DAI pins (DAI_P07 – DAI_P20).
Switching Characteristics
PCG Output Clock and Frame Sync Active Edge Delay After PCG Input tDPCGIOClock Falling Edge2.5
tDTRIGPCG Output Clock and Frame Sync Delay After PCG Trigger2.5 + 2.5 × tPCGOWOutput Clock Pulse Width40tPCGOW10ns
10 + 2.5 × tPCGOWns
ns
tSTRIGDAI_PnPCG_TRIGx_ItHTRIGDAI_PmPCG_EXTx_I(CLKIN)DAI_PyPCG_CLKx_OtDPCGIOtPCGOWDAI_PzPCG_FSx_OtDTRIGtPCGIWFigure 15.Precision Clock Generator (Direct Pin Routing)
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ADSP-21266
Flags
The timing specifications in Table19 and Figure16 apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table3 on Page11 for more informa-tion on flag use.Table 19.Flags
Parameter
Timing RequirementtFIPWFLAG3–0 IN Pulse WidthSwitching CharacteristictFOPWFLAG3–0 OUT Pulse Width
Min2 × tCCLK + 3
Max
Unitns
2 × tCCLK – 1ns
DAI_P20–1(FLAG3–0IN)(AD15–0)tFIPWDAI_P20–1(FLAG3–0OUT)(AD15–0)tFOPWFigure 16.Flags
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ADSP-21266
Memory Read—Parallel Port
The specifications in Table20, Table21, Figure17, and
Figure18 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21266 is access-ing external memory space.
Table 20.8-Bit Memory Read Cycle
Parameter
Timing RequirementstDRSAddress/Data 7–0 Setup Before RD HightDRHAddress/Data 7–0 Hold After RD High Address 15–8 to Data ValidtDADSwitching Characteristics
ALE Pulse WidthtALEWtALERWALE Deasserted to Read/Write AssertedtADASAddress/Data 15–0 Setup Before ALE Deasserted1tADAHAddress/Data 15–0 Hold After ALE Deasserted1 tALEHZ ALE Deasserted1 to Address/Data[7:0] In High ZtRWRD Pulse Width Address/Data 15–8 Hold After RD High tADRH D = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1Min3.30
MaxUnitnsnsns
D + 0.5 × tCCLK – 3.5
2 × tCCLK – 21 × tCCLK – 0.52.5 × tCCLK – 2.00.5 × tCCLK – 0.80.5 × tCCLK – 0.8D – 2
0.5 × tCCLK – 1 + H
0.5 × tCCLK + 2.0
nsnsnsnsnsnsns
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEtALEWtALERWRDtRWWRtALEHZtADAStADAHtADRHAD15-8VALIDADDRESSVALIDADDRESStDRStDRHAD7-0VALIDADDRESStDADVALIDDATAFigure 17.8-Bit Memory Read Cycle
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ADSP-21266
Table 21.16-Bit Memory Read Cycle
Parameter
Timing RequirementstDRStDRHMin
Address/Data 15–0 Setup Before RD highAddress/Data 15–0 Hold After RD high3.30
Max
Unitnsnsnsnsnsnsnsnsns
Switching CharacteristicstALEWALE Pulse Width
ALE Deasserted to Read/Write AssertedtALERWtADASAddress/Data 15–0 Setup Before ALE Deasserted1tADAHAddress/Data 15–0 Hold After ALE Deaserted1tALEHZALE Deasserted1 to Address/Data 15–0 In High ZtRWRD Pulse WidthD = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
12 × tCCLK – 2 1 × tCCLK – 0.52.5 × tCCLK – 2.00.5 × tCCLK – 0.80.5 × tCCLK – 0.8D – 2
0.5tCCLK + 2.0
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEtALEWtALERWRDtRWWRtADASAD15-0VALIDADDRESStADAHtDRStDRHVALIDDATAtALEHZFigure 18.16-Bit Memory Read Cycle
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ADSP-21266
Memory Write—Parallel Port
Use the specifications in Table22, Table23, Figure19, and Figure20 for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-21266 is access-ing external memory space.
Table 22.8-Bit Memory Write Cycle
Parameter
Switching CharacteristicstALEWALE Pulse WidthtALERWALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted1tADAStADAHAddress/Data 15–0 Hold After ALE Deasserted1tWWWR Pulse WidthtADWLAddress/Data 15–8 to WR LowtADWHAddress/Data 15–8] Hold After WR HightALEHZALE Deasserted1 to Address/Data 15–0 In High Z
Address/Data 7–0 Setup Before WR High tDWStDWH Address/Data 7–0 Hold After WR HightDAWHAddress/Data to WR HighD = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1Min
2 × tCCLK – 21 × tCCLK – 0.52.5 × tCCLK – 2.00.5 × tCCLK – 0.8D – 2
0.5 × tCCLK – 1.50.5 × tCCLK – 1 + H0.5 × tCCLK – 0.8D
0.5 × tCCLK – 1.5 + H D
MaxUnitnsnsnsnsnsnsnsnsnsnsns
0.5tCCLK + 2.0
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
tALERWALEtALEWtDAWHWRtWWRDtALEHZtADAStADAHtADWLtADWHAD15-8VALIDADDRESSVALIDADDRESStDWStDWHAD7-0VALIDADDRESSVALIDDATAFigure 19.8-Bit Memory Write Cycle
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ADSP-21266
Table 23.16-Bit Memory Write Cycle
Parameter
Switching CharacteristicstALEWALE Pulse Width
ALE Deasserted to Read/Write AssertedtALERWtADASAddress/Data 15–0 Setup Before ALE Deasserted1tADAHAddress/Data 15–0 Hold After ALE Deasserted1tWWWR Pulse WidthtALEHZALE Deasserted1 to Address/Data 15–0 In High ZtDWSAddress/Data 15–0 Setup Before WR HightDWHAddress/Data 15–0 Hold After WR HighD = (data cycle duration) × tCCLK
H = tCCLK (if a hold cycle is specified, else H = 0)
1Min
2 × tCCLK – 21 × tCCLK – 0.52.5 × tCCLK – 2.00.5 × tCCLK – 0.8 D – 2
0.5 × tCCLK – 0.8D
0.5 × tCCLK – 1.5 + H
MaxUnitnsnsnsnsnsnsnsns
0.5tCCLK + 2.0
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEtALEWtALERWWRtWWRDtALEHtADASAD15-0tADAHtDWStDWHVALIDADDRESSVALIDDATAFigure 20.16-Bit Memory Write Cycle
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ADSP-21266
Serial Ports
To determine whether communication is possible between two devices at clock speed n, the specifications in Table24, Table25, Table26, Table27, Figure21, and Figure22 must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width.Table 24.Serial Ports—External Clock
Parameter
Timing RequirementstSFSEFS Setup Before SCLK
1(Externally Generated FS in Either Transmit or Receive Mode)
tHFSEFS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1Receive Data Setup Before Receive SCLK1tSDREtHDREReceive Data Hold After SCLK1tSCLKWSCLK WidthtSCLKSCLK PeriodSwitching CharacteristicstDFSEFS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2tHOFSEFS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2tDDTETransmit Data Delay After Transmit SCLK2tHDTETransmit Data Hold After Transmit SCLK212Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifi-cations provided below are valid at the DAI_P20–1 pins.
MinMaxUnit
2.52.52.52.5720
ns ns ns ns ns ns
7
2
7
2
ns nsns ns
Referenced to sample edge.Referenced to drive edge.
Table 25.Serial Ports—Internal Clock
Parameter
Timing RequirementstSFSIFS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1tHFSIFS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)1tSDRIReceive Data Setup Before SCLK1tHDRIReceive Data Hold After SCLK1Switching CharacteristicstDFSIFS Delay After SCLK (Internally Generated FS in Transmit Mode)2tHOFSIFS Hold After SCLK (Internally Generated FS in Transmit Mode)2tDFSIFS Delay After SCLK (Internally Generated FS in Receive Mode)2FS Hold After SCLK (Internally Generated FS in Receive Mode)2tHOFSItDDTITransmit Data Delay After SCLK2tHDTITransmit Data Hold After SCLK2tSCLKIWTransmit or Receive SCLK Width
12MinMaxUnit
61.5
61.5
ns ns ns ns
3
–1.0
3
–1.0
3
–1.0
0.5tSCLK – 2
0.5tSCLK + 2ns nsnsnsns ns ns
Referenced to the sample edge.Referenced to drive edge.
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ADSP-21266
Table 26.Serial Ports—Enable and Three-State
Parameter
Switching CharacteristicstDDTENData Enable from External Transmit SCLK1Data Disable from External Transmit SCLK1tDDTTEtDDTINData Enable from Internal Transmit SCLK11Min2
MaxUnitns
ns ns
7
–1
Referenced to drive edge.
Table 27.Serial Ports—External Late Frame Sync
ParameterMinSwitching CharacteristicstDDTLFSEData Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 01tDDTENFSData Enable for MCE = 1, MFD = 010.5
1MaxUnit
7
ns
ns
The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNALRECEIVEFSWITHMCE=1,MFD=0DAI_P20-1(SCLK)DRIVESAMPLEDRIVEtSFSE/IDAI_P20-1(FS)tHFSE/ItDDTENFSDAI_P20-1(DATACHANNELA/B)tDDTE/ItHDTE/I1STBIT2NDBITtDDTLFSELATEEXTERNALTRANSMITFSDRIVESAMPLEDRIVEDAI_P201(SCLK)tSFSE/IDAI_P20-1(FS)tHFSE/ItDDTENFSDAI_P20-1(DATACHANNELA/B)tDDTE/ItHDTE/I1STBIT2NDBITtDDTLFSENOTE:SERIALPORTSIGNALS(SCLK,FS,DATACHANNELA/B)AREROUTEDTOTHEDAI_P[20:1]PINSUSINGTHESRU.THETIMINGSPECIFICATIONSPROVIDEDHEREAREVALIDATTHEDAI_P[20:1]PINS.Figure 21.External Late Frame Sync11This figure reflects changes made to support left-justified sample pair mode.
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ADSP-21266
DATARECEIVE—INTERNALCLOCKDRIVEEDGESAMPLEEDGEDATARECEIVE—EXTERNALCLOCKDRIVEEDGESAMPLEEDGEtSCLKIWDAI_P20–1(SCLK)DAI_P20–1(SCLK)tSCLKWtDFSItHOFSIDAI_P20–1(FS)tSFSItHFSIDAI_P20–1(FS)tDFSEtHOFSEtSFSEtHFSEtSDRIDAI_P20–1(DATACHANNELA/B)tHDRIDAI_P20–1(DATACHANNELA/B)tSDREtHDRENOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFSCLK(EXTERNAL),SCLK(INTERNAL)CANBEUSEDASTHEACTIVESAMPLINGEDGE.DATATRANSMIT—INTERNALCLOCKDRIVEEDGESAMPLEEDGEDATATRANSMIT—EXTERNALCLOCKDRIVEEDGESAMPLEEDGEtSCLKIWDAI_P20–1(SCLK)DAI_P20–1(SCLK)tSCLKWtDFSItHOFSIDAI_P20–1(FS)tSFSItHFSIDAI_P20–1(FS)tDFSEtHOFSEtSFSEtHFSEtHDTIDAI_P20–1(DATACHANNELA/B)tDDTIDAI_P20–1(DATACHANNELA/B)tHDTEtDDTENOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFSCLK(EXTERNAL),SCLK(INTERNAL)CANBEUSEDASTHEACTIVESAMPLINGEDGE.DRIVEEDGEDAI_P20–1SCLK(EXT)DRIVEEDGESCLKtDDTENtDDTTEDAI_P20–1(DATACHANNELA/B)DRIVEEDGEDAI_P20–1SCLK(INT)tDDTINDAI_P20–1(DATACHANNELA/B)Figure 22.Serial Ports
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ADSP-21266
Input Data Port (IDP)
The timing requirements for the IDP are given in Table28 and Figure23. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifi-cations provided below are valid at the DAI_P20–1 pins.Table 28.Input Data Port (IDP)
Parameter
Timing RequirementstSISFSFS Setup Before SCLK Rising Edge1tSIHFSFS Hold After SCLK Rising Edge1SData Setup Before SCLK Rising Edge1tSISDtSIHDSData Hold After SCLK Rising Edge1tIDPCLKWClock WidthtIDPCLKClock Period
1Min2.5
2.52.52.5720
MaxUnitns ns ns ns ns ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either CLKIN or any of the DAI pins.
SAMPLEEDGEtIDPCLKWDAI_P20–1(SCLK)tSIHFStSISFSDAI_P20–1(FS)tSISDDAI_P20–1(SDATA)tSIHDFigure 23.Input Data Port (IDP)
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ADSP-21266
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in Table29 and Figure24. PDAP is the parallel mode operation of
Channel0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 29.Parallel Data Acquisition Port (PDAP)
Parameter
Timing RequirementstSPCLKENPDAP_CLKEN Setup Before PDAP_CLK Sample Edge1tHPCLKENPDAP_CLKEN Hold After PDAP_CLK Sample Edge1PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1tPDSDtPDHDPDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1tPDCLKWClock WidthtPDCLKClock Period
Switching CharacteristicstPDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a WordtPDSTRBPDAP Strobe Pulse Width
1Note that the most significant 16 bits of external PDAP data can
be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins.
Min2.52.52.52.5720
MaxUnitnsns ns ns ns ns
2 × tCCLK1 × tCCLK – 1ns ns
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SAMPLEEDGEtPDCLKtPDCLKWDAI_P20–1(PDAP_CLK)tSPCLKENDAI_P20–1(PDAP_CLKEN)tHPCLKENtPDSDDATAtPDHDDAI_P20–1(PDAP_STROBE)tPDSTRBtPDHLDDFigure 24.Parallel Data Acquisition Port (PDAP)
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ADSP-21266
SPI Interface Protocol—MasterTable 30.SPI Interface Protocol—Master
Parameter
Timing RequirementstSSPIDMData Input Valid to SPICLK Edge (Data Input Setup Time)tHSPIDMSPICLK Last Sampling Edge to Data Input Not ValidSwitching CharacteristicstSPICLKMSerial Clock Cycle tSPICHMSerial Clock High Period tSPICLMSerial Clock Low Period tDDSPIDMSPICLK Edge to Data Out Valid (Data Out Delay Time)tHDSPIDMSPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0 OUT (SPI Device Select) Low to First SPICLK EdgetSDSCIMtHDSMLast SPICLK Edge to FLAG3–0 OUT HightSPITDMSequential Transfer Delay
Min5
2
Max
Unitnsns
8 × tCCLK4 × tCCLK – 24 × tCCLK – 2
3
10
4 × tCCLK – 24 × tCCLK – 14 × tCCLK – 1nsnsnsnsnsnsnsns
FLG3-0(OUTPUT)tSDSCIMSPICLK(CP=0)(OUTPUT)tSPICHMtSPICLMtSPICLKMtHDSMtSPITDMtSPICLMSPICLK(CP=1)(OUTPUT)tSPICHMtDDSPIDMMOSI(OUTPUT)CPHASE=1MISO(INPUT)MSBVALIDMSBtHDSPIDMLSBtSSPIDMtHSPIDMtSSPIDMLSBVALIDtHSPIDMtDDSPIDMMOSI(OUTPUT)CPHASE=0MISO(INPUT)MSBtHDSPIDMLSBtSSPIDMMSBVALIDtHSPIDMLSBVALIDFigure 25.SPI Interface Protocol—Master
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ADSP-21266
SPI Interface Protocol—SlaveSee Table31 and Figure26.
Table 31.SPI Interface Protocol—Slave
Parameter
Timing RequirementstSPICLKStSPICHStSPICLStSDSCOMin
Serial Clock Cycle
Serial Clock High Period Serial Clock Low Period
SPIDS Assertion to First SPICLK EdgeCPHASE = 0CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0Data Input Valid to SPICLK Edge (Data Input Setup Time)SPICLK Last Sampling Edge to Data Input Not ValidSPIDS Deassertion Pulse Width (CPHASE = 0)4 × tCCLK2 × tCCLK – 22 × tCCLK – 22 × tCCLK + 12 × tCCLK + 12 × tCCLK22
2 × tCCLK00
2 × tCCLK – 2
5 × tCCLK + 2557.5Max
Unitnsnsnsnsnsnsnsnsnsnsnsnsnsns
tHDStSSPIDStHSPIDStSDPPWSwitching CharacteristicstDSOESPIDS Assertion to Data Out ActivetDSDHISPIDS Deassertion to Data High ImpedancetDDSPIDSSPICLK Edge to Data Out Valid (Data Out Delay Time)tHDSPIDSSPICLK Edge to Data Out Not Valid (Data Out Hold Time)tDSOVSPIDS Assertion to Data Out Valid (CPHASE = 0)SPIDS(INPUT)tSPICHSSPICLK(CP=0)(INPUT)tSPICLStSPICLKStHDStSDPPWtSDSCOSPICLK(CP=1)(INPUT)tSPICLStSPICHStDSOEtDDSPIDStDSDHItDDSPIDSMSBLSBtHDSPIDSMISO(OUTPUT)CPHASE=1MOSI(INPUT)tSSPIDSMSBVALIDtHSPIDStSSPIDSLSBVALIDtDSOVtDSOEMISO(OUTPUT)CPHASE=0MOSI(INPUT)MSBVALIDMSBtDDSPIDStHDSPIDSLSBtDSDHItSSPIDSLSBVALIDtHSPIDSFigure 26.SPI Interface Protocol—Slave
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ADSP-21266
JTAG Test Access Port and EmulationSee Table32 and Figure27.
Table 32.JTAG Test Access Port and Emulation
Parameter
Timing RequirementstTCKTCK PeriodtSTAPTDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK HightHTAPtSSYSSystem Inputs Setup Before TCK High1tHSYSSystem Inputs Hold After TCK High1tTRSTWTRST Pulse WidthSwitching CharacteristicstDTDOTDO Delay from TCK LowtDSYSSystem Outputs Delay After TCK Low212Min20
56784tCKMaxUnitnsnsnsnsnsns
710nsns
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
tTCKTCKtSTAPTMSTDItDTDOTDOtSSYSSYSTEMINPUTStDSYSSYSTEMOUTPUTStHSYStHTAPFigure 27.JTAG Test Access Port and Emulation
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ADSP-21266
OUTPUT DRIVE CURRENTS
Figure28 shows typical I-V characteristics for the output driv-ers of the ADSP-21266. The curves represent the current drive capability of the output drivers as a function of output voltage.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure29). Figure32 shows graphically how output delays and holds vary with load capacitance (note that this graph or derating does not apply to output disable delays). The graphs of Figure31, Figure32, and Figure33 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20%–80%, V=Min) vs. Load Capacitance.
4030SOURCE(VDDEXT)CURRENT(mA)VOH3.3V,25°C3.47V,–45°C201003.11V,125°C1210RISEANDFALLTIMES(ns)–103.11V,125°C–203.3V,25°C–30–400VOL3.47V,–45°C0.511.522.5SWEEP(VDDEXT)VOLTAGE(V)33.5y=0.0467x+1.63238RISEFALL64y=0.045x+1.524Figure 28.Typical Drive
2TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table11 on Page19 through Table32 on Page36. These include output disable time, output enable time, and capacitive loading. Timing is measured on signals when they cross the 1.5V level as described in Figure30. All delays (in nanoseconds) are mea-sured between the point that the first signal reaches 1.5V and the point that the second signal reaches 1.5V.
RISEANDFALLTIMES(ns)0050100150200250LOADCAPACITANCE(pF)Figure 31.Typical Output Rise Time
(20%–80%, VDDEXT = Max)
12RISE10y=0.049x+1.51058FALLTOOUTPUTPIN30pF50⍀1.5V6y=0.0482x+1.460442Figure 29.Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
0050100150200250LOADCAPACITANCE(pF)INPUTOROUTPUT1.5V1.5VFigure 32.Typical Output Rise/Fall Time
(20%–80%, VDDEXT = Min)
Figure 30.Voltage Reference Levels for AC Measurements
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ADSP-21266
where:
108OUTPUTDELAYORHOLD(ns)TA = ambient temperature °C
Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required.
Y=0.0488X–1.59236420–2–40Table 33.Thermal Characteristics for 136-Ball BGA ParameterθJAθJMAθJMAθJCΨJTΨJMTΨJMTConditionAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/sAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/sTypical31.027.326.06.990.160.300.35Unit°C/W°C/W°C/W°C/W°C/W°C/W°C/W50100LOADCAPACITANCE(pF)150200Table 34.Thermal Characteristics for 144-Lead LQFP Figure 33.Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
ENVIRONMENTAL CONDITIONS
The ADSP-21266 processor is rated for performance under TAMB environmental conditions specified in the Recommended Operating Conditions on Page15.
ParameterθJAθJMAθJMAθJCΨJTΨJMTΨJMTAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/sAirflow = 0 m/sAirflow = 1 m/sAirflow = 2 m/sTypical32.528.927.87.80.50.81.0Unit°C/W°C/W°C/W°C/W°C/W°C/W°C/WTHERMAL CHARACTERISTICS
Table33 and Table34 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883. All measure-ments use a 2S2P JEDEC test board.
To determine the junction temperature of the device while on the application PCB, use
TJ=TCASE+(ΨJT×PD)where:
TJ = junction temperature (°C)
TCASE = case temperature (°C) measured at the top center of the package
ΨJT = junction-to-top (of package) characterization parameter is the typical value from Table33 and Table34.PD = power dissipation (see EE Note No. 216)
Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first order approxi-mation of TJ by the equation
TJ=TA+(θJA×PD)Rev. B|Page 38 of 44|May 2005
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ADSP-21266
136-BALL BGA PIN CONFIGURATIONSTable35 shows the ADSP-21266’s pin names and their default function after reset (in parentheses). Figure34 on Page41 shows the BGA package pin assignments.Table 35.136-Ball BGA Pin Assignments
Pin NameCLKCFG0XTALTMSTCKTDI
CLKOUTTDOEMUMOSIMISOSPIDSVDDINTGNDGNDVDDINTGNDGNDGNDGNDGNDGNDGNDGNDFLAG3
BGA Pin No.A01A02A03A04A05A06A07A08A09A10A11A12A13A14E01E02E04E05E06E09E10E11E13E14
Pin NameCLKCFG1GNDVDDEXTCLKINTRSTAVSSAVDDVDDEXTSPICLKRESETVDDINTGNDGNDGNDFLAG1FLAG0GNDGNDGNDGNDGNDGNDFLAG2
DAI_P20 (SFS45)
BGA Pin No.B01B02B03B04B05B06B07B08B09B10B11B12B13B14F01F02F04F05F06F09F10F11F13F14
Pin NameBOOTCFG1BOOTCFG0GNDGNDGNDVDDINTBGA Pin No.C01C02C03C12C13C14
Pin NameVDDINTGNDGNDGNDGNDGNDGNDGNDGNDVDDINTBGA Pin No.D01D02D04D05D06D09D10D11D13D14
AD7VDDINTVDDEXTDAI_P19 (SCLK45)G01G02G13G14AD6VDDEXTDAI_P18 (SD5B)DAI_P17 (SD5A)H01H02H13H14
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ADSP-21266
Table 35.136-Ball BGA Pin Assignments (Continued)
Pin NameAD5AD4GNDGNDGNDGNDGNDGNDVDDINTDAI_P16 (SD4B)AD15ALERDVDDINTVDDEXTAD8VDDINTDAI_P2 (SD0B)VDDEXTDAI_P4 (SFS0)VDDINTVDDINTGND
DAI_P10 (SD2B)
BGA Pin No.J01J02J04J05J06J09J10J11J13J14N01N02N03N04N05N06N07N08N09N10N11N12N13N14
Pin NameAD3VDDINTGNDGNDGNDGNDGNDGNDGND
DAI_P15 (SD4A)AD14AD13AD12AD11AD10AD9
DAI_P1 (SD0A)DAI_P3 (SCLK0)DAI_P5 (SD1A)DAI_P6 (SD1B)DAI_P7 (SCLK1)DAI_P8 (SFS1)DAI_P9 (SD2A)DAI_P11 (SD3A)
BGA Pin No.K01K02K04K05K06K09K10K11K13K14P01P02P03P04P05P06P07P08P09P10P11P12P13P14
Pin NameAD2AD1GNDGNDGNDGNDGNDGNDGND
DAI_P14 (SFS23)
BGA Pin No.L01L02L04L05L06L09L10L11L13L14
Pin NameAD0WRGNDGND
DAI_P12 (SD3B)DAI_P13 (SCLK23)
BGA Pin No.M01M02M03M12M13M14
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ADSP-21266
1413121110987654321ABCDEFGHJKLMNPKEYVDDINTVDDEXTGNDAVSSAVDDI/OSIGNALS*USETHECENTERBLOCKOFGROUNDPINSTOPROVIDETHERMALPATHWAYSTOYOURPRINTEDCIRCUITBOARD’SGROUNDPLANE.Figure 34.136-Ball BGA Pin Assignments (Bottom View, Summary)
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ADSP-21266
144-LEAD LQFP PIN CONFIGURATIONSTable36 shows the ADSP-21266’s pin names and their default function after reset (in parentheses).Table 36.144-Lead LQFP Pin Assignments
Pin NameVDDINTCLKCFG0CLKCFG1BOOTCFG0BOOTCFG1GNDVDDEXTGNDVDDINTGNDVDDINTGNDVDDINTGNDFLAG0FLAG1AD7GNDVDDINTGNDVDDEXTGNDVDDINTAD6AD5AD4VDDINTGNDAD3AD2VDDEXTGNDAD1AD0WRVDDINTLQFP Pin No.Pin Name1VDDINT2GND3RD4ALE5AD156AD147AD138GND9VDDEXT10AD1211VDDINT12GND13AD1114AD1015AD916AD817DAI_P1 (SD0A)18 VDDINT19GND20DAI_P2 (SD0B)21DAI_P3 (SCLK0)22GND23VDDEXT24VDDINT25GND26DAI_P4 (SFS0)27DAI_P5 (SD1A)28DAI_P6 (SD1B)29DAI_P7 (SCLK1)30VDDINT31GND32VDDINT33GND34DAI_P8 (SFS1)35DAI_P9 (SD2A)36VDDINTLQFP LQFP
Pin No.Pin NamePin No.Pin Name37VDDEXT73GND
I38GND74VDDINT39VDDINT75GND40GND76 VDDINT41DAI_P10 (SD2B)77GND42DAI_P11 (SD3A)78VDDINT43DAI_P12 (SD3B)79GND44 DA_P13 (SCLK23)80VDDEXTI45DAI_P14 (SFS23)81GND46DAI_P15 (SD4A)82VDDINT47VDDINT83GND48GND84VDDINT49GND85RESET50DAI_P16 (SD4B)86SPIDS51DAI_P17 (SD5A)87GND52DAI_P18 (SD5B)88VDDINT53DAI_P19 (SCLK45)89SPICLK54VDDINT90MISO55 GND91MOS56GND92GND57VDDEXT93VDDINT58DAI_P20 (SFS45)94VDDEXT59GND95AVDD60VDDINT96AVSS61FLAG297GND62FLAG398CLKOUT63VDDINT99EMU64GND100TDO
101TDI65VDDINT66GND102TRST67VDDINT103TCK68GND104TMS69 VDDINT105GND70GND106 CLKIN71VDDINT107XTAL72VDDINT108VDDEXTLQFP
Pin No.109110111112113114115116117118119120121122123124125126127128 129130131132133134135136137138139140141142143144
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ADSP-21266
PACKAGE DIMENSIONSThe ADSP-21266 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure35 and Figure36.
12.00BSCSQ0.80BSCTYP10.40BSCSQPINA1INDICATORABCDEFGHJKLMNP14131211109876543210.80BSCTYPTOPVIEW1.70MAXDETAILABOTTOMVIEW1.DIMENSIONSAREINMILIMETERS(MM).2.THEACTUALPOSITIONOFTHEBALLGRIDISWITHIN0.15MMOFITSIDEALPOSITIONRELATIVETOTHEPACKAGEEDGES.3.COMPLIANTTOJEDECSTANDARDMO-205-AE,EXCEPTFORTHEBALLDIAMETER.4.CENTERDIMENSIONSARENOMINAL.0.25MIN0.500.450.40(BALLDIAMETER)DETAILASEATINGPLANE0.12MAX(BALLCOPLANARITY)Figure 35.136-Ball BGA (BC-136-3)
22.00BSCSQ20.00BSCSQ1441109108PIN1INDICATOR0.270.22TYP0.17SEATINGPLANE0.08MAX(LEADCOPLANARITY)0.150.051.451.401.351.60MAX1.DIMENSIONSAREINMILLIMETERSANDCOMPLYWITHJEDECSTANDARDMS-026-BFB.2.ACTUALPOSITIONOFEACHLEADISWITHIN0.08OFITSIDEALPOSITIONWHENMEASUREDINTHELATERALDIRECTION.3.CENTERDIMENSIONSARENOMINAL.0.50BSCTYP(LEADPITCH)0.750.60TYP0.4536733772DETAILADETAILATOPVIEW(PINSDOWN)Figure 36.144-Lead LQFP (ST-144-2)
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ADSP-21266
ORDERING GUIDE
Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21266 DSP. For a complete list, visit our website at www.analog.com/SHARC.
Ambient Temper-Part Number ature RangeADSP-21266SKSTZ-1B0°C to +70°CADSP-21266SKSTZ-2B0°C to +70°CADSP-21266SKBCZ-2B0°C to +70°CADSP-21266SKBC-2B0°C to +70°CADSP-21266SKSTZ-1C 0°C to +70°CADSP-21266SKSTZ-2C 0°C to +70°CADSP-21266SKBCZ-2C0°C to +70°CADSP-21266SKSTZ-2D0°C to +70°CADSP-21266SKBCZ-2D0°C to +70°C
1,2,3,4,512On-Chip
Instruction Rate SRAM150 MHz2M bit200 MHz2M bit200 MHz2M bit200 MHz2M bit150 MHz2M bit200 MHz2M bit200 MHz2M bit200 MHz2M bit200 MHz2M bit
ROM
4M bit 4M bit 4M bit 4M bit 4M bit 4M bit 4M bit 4M bit 4M bit
Operating Voltage
1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V1.2 INT/3.3 EXT V
Package
144-Lead LQFP; Pb-free144-Lead LQFP; Pb-free136-Ball BGA; Pb-free136-Ball BGA
144-Lead LQFP; Pb-free144-Lead LQFP; Pb-free136-Ball BGA; Pb-free144-Lead LQFP; Pb-free136-Ball BGA; Pb-free
K in part number indicates commercial grade ambient temperature range.
ST indicates Low Profile Quad Flat package. BC indicates Ball Grid Array package. .3Z = Pb-free part. For more information about lead-free package offerings, please visit www.analog.com.4B at end of part number indicates Rev. 0.1 silicon. See Table2 on Page6 for multichannel surround-sound decoder algorithms in on-chip B ROM.5C and D at end of part number indicate Rev. 0.2 silicon. See Table2 on Page6 for multichannel surround-sound decoder algorithms in on-chip C and D ROM.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D03758-0-5/05(B)
Rev. B|Page 44 of 44|May 2005
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