ADS1625ADS1626SBAS280E − JUNE 2003 − REVISED MAY 200718ĆBit, 1.25MSPSAnalogĆtoĆDigital ConverterFEATURESDData Rate: 1.25MSPSDSignal-to-Noise Ratio: 93dBDTotal Harmonic Distortion: −101dBDSpurious-Free Dynamic Range: 103dBDLinear Phase with 615kHz BandwidthDPassband Ripple: ±0.0025dBDAdjustable FIFO Output Buffer (ADS1626 only)DSelectable On-Chip ReferenceDDirectly Connects to TMS320C6000 DSPsDAdjustable Power Dissipation: 150 to 515mWDPower Down ModeDSupplies:Analog +5VDigital +3VDigital I/O +2.7V to +5.25VDESCRIPTIONThe ADS1625 and ADS1626 are high-speed, high-precision,delta-sigma analog-to-digital converters (ADCs) with 18-bitresolution. The data rate is 1.25 mega samples per second(MSPS), the bandwidth (−3dB) is 615kHz, and passbandripple is less than ±0.0025dB (to 550kHz). Both devices offerthe same outstanding performance at these speeds with asignal-to-noise ratio up to 93dB, total harmonic distortiondown to −101dB, and a spurious-free dynamic range up to103dB. The ADS1626 includes an adjustable first-in, first-outbuffer (FIFO) for the output data.The input signal is measured against a voltage reference thatcan be generated on-chip or supplied externally. The digitaloutput data are provided over a simple parallel interface thateasily connects to digital signal processors (DSPs). Anout-of-range monitor reports when the input range has beenexceeded. The ADS1625/6 operate from a +5V analogsupply (AVDD) and +3V digital supply (DVDD). The digitalI/O supply (IOVDD) operates from +2.7 to +5.25V, enablingthe digital interface to support a range of logic families. Theanalog power dissipation is set by an external resistor andcan be reduced when operating at slower speeds. Apower-down mode, activated by a digital I/O pin, shuts downall circuitry. The ADS1625/6 are offered in a TQFP-64package using TI PowerPAD technology.The ADS1625 and ADS1626, along with their 16-bit,5MSPS counterparts, the ADS1605 and ADS1606, arewell-suited for the demanding measurement requirementsof scientific instrumentation, automated test equipment,data acquisition, and medical imaging.APPLICATIONSDScientific InstrumentsDAutomated Test EquipmentDData AcquisitionDMedical ImagingDVibration AnalysisVREFPVREFNVMIDRBIASVCAPAVDDDVDDIOVDDReferenceandBiasCircuitsAINPAINN∆ΣModulatorDigitalFilterI/OInterfacePDREFENRESETCLKCSRDDRDYOTRADS1626OnlyFIFOADS1625ADS1626AGNDDGNDDOUT[17:0]FIFO_LEV[2:0]Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Productsconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.Copyright 2003−2007, Texas Instruments Incorporatedhttp://oneic.com/www.ti.comADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007ORDERING INFORMATIONPRODUCTPACKAGE−LEADPACKAGEDESIGNATOR(1)PAPPAPSPECIFIEDTEMPERATURERANGE−40°C to +85°C−40°C to +85°CPACKAGEMARKINGADS1625IADS1626IORDERINGNUMBERADS1625IPAPTADS1625IPAPRADS1626IPAPTADS1626IPAPRTRANSPORTMEDIA, QUANTITYTape and Reel, 250Tape and Reel, 1000Tape and Reel, 250Tape and Reel, 1000ADS1625ADS1626HTQFP−64HTQFP−64(1)For the most current specifications and package information, refer to our web site at www.ti.com.ABSOLUTE MAXIMUM RATINGSPRODUCT FAMILYPRODUCTADS1605ADS1606ADS1625ADS1626RESOLUTION16 Bits16 Bits18 Bits18 BitsDATA RATE5.0MSPS5.0MSPS1.25MSPS1.25MSPSFIFO?NoYesNoYesUNITVVVVmAmAVV°C°C°Cover operating free-air temperature range unless otherwise noted(1)ADS1625/26AVDD to AGNDDVDD to DGNDIOVDD to DGNDAGND to DGNDInput CurrentInput CurrentAnalog I/O to AGNDDigital I/O to DGNDMaximum Junction TemperatureOperating Temperature RangeStorage Temperature Range−0.3 to +6−0.3 to +3.6−0.3 to +6−0.3 to +0.3100, Momentary10, Continuous−0.3 to AVDD + 0.3−0.3 to IOVDD + 0.3+150−40 to +105−60 to +150This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures cancause damage.ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changescould cause the device not to meet its published specifications.Lead Temperature (soldering, 10s)+260°C(1)Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periodsmay degrade device reliability. These are stress ratings only, andfunctional operation of the device at these or any other conditionsbeyond those specified is not implied.2http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007ELECTRICAL CHARACTERISTICS All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, FIFO disabled, andRBIAS = 37kΩ, unless otherwise noted.PARAMETERAnalog Input0dBFSDifferential input voltage (VIN)(AINP − AINN)Common-mode input voltage (VCM)(AINP + AINN) / 2Absolute input voltage(AINP or AINN with respect to AGND)Dynamic SpecificationsData ratefIN = 10kHz, −2dBFSfIN = 10kHz, −6dBFSfIN = 10kHz, −20dBFSfIN = 100kHz, −2dBFSSignal-to-noise ratio (SNR)fIN = 100kHz, −6dBFSfIN = 100kHz, −20dBFSfIN = 500kHz, −2dBFSfIN = 500kHz, −6dBFSfIN = 500kHz, −20dBFSfIN = 10kHz, −2dBFSfIN = 10kHz, −6dBFSfIN = 10kHz, −20dBFSTotal harmonic distortion (THD)fIN = 100kHz, −2dBFSfIN = 100kHz, −6dBFSfIN = 100kHz, −20dBFSfIN = 500kHz, −2dBFSfIN = 500kHz, −6dBFSfIN = 500kHz, −20dBFSfIN = 10kHz, −2dBFSfIN = 10kHz, −6dBFSfIN = 10kHz, −20dBFSfIN = 100kHz, −2dBFSSignal-to-noise and distortion (SINAD)fIN = 100kHz, −6dBFSfIN = 100kHz, −20dBFSfIN = 500kHz, −2dBFSfIN = 500kHz, −6dBFSfIN = 500kHz, −20dBFS69701.25TEST CONDITIONSMINTYP±1.467VREF±1.165VREF±0.735VREF±0.147VREF2.0MAXUNITVVVVV−2dBFS−6dBFS−20dBFS0dBFS−2dBFS input and smaller−0.10.14.74.2VVǒfCLK40MHzǓMSPSdBdBdBdBdBdBdBdBdBdBdBdBdBdB−90dBdBdBdBdBdBdBdBdBdBdBdBdB939076939076939076−101−103−96−95−101−98−114−110−969289769189769390763http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007ELECTRICAL CHARACTERISTICS (continued)All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, FIFO disabled, andRBIAS = 37kΩ, unless otherwise noted.PARAMETERTEST CONDITIONSfIN = 10kHz, −2dBFSfIN = 10kHz, −6dBFSfIN = 10kHz, −20dBFSfIN = 100kHz, −2dBFSSpurious-free dynamic range (SFDR)fIN = 100kHz, −6dBFSfIN = 100kHz, −20dBFSfIN = 500kHz, −2dBFSfIN = 500kHz, −6dBFSfIN = 500kHz, −20dBFSIntermodulation distortion (IMD)Aperture delayDigital Filter CharacteristicsPassbandPassband ripple−0.1dB attenuationPassband transition−3.0dB attenuationStop bandStop band attenuationGroup delay615575MINTYP1041069997103MAXUNITdBdBdBdBdBdBdBdBdBdBns9210212011399−984f1 = 495kHz, −2dBFSf2 = 505kHz, −2dBFS0550ǒfCLK40MHzǓkHzdBkHzkHz± 0.0025ǒǒfCLK40MHzfCLK40MHzǓǓ39.30.7ǒfCLK40MHzǓ20.8ǒfCLK40MHzǓMHzdB72Settling timeStatic SpecificationsResolutionNo missing codesInput referred noiseIntegral nonlinearityDifferential nonlinearityOffset errorOffset error driftGain errorGain error driftCommon-mode rejectionPower-supply rejectionTo ±0.001%36.8ǒǒ40MHzfCLK40MHzfCLKǓǓµsµs18181.5−2.0dBFS signal3.5±0.50.0510.25Excluding reference driftat DCat DC107565BitsBitsLSB, rmsLSBLSB%FSRppmFSR/°C%ppm/°CdBdB4http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007ELECTRICAL CHARACTERISTICS (continued)All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, FIFO disabled, andRBIAS = 37kΩ, unless otherwise noted.PARAMETERVoltage Reference(1)VREF = (VREFP − VREFN)VREFPVREFNVMIDVREF driftStartup timeClock InputFrequency (fCLK)Duty CycleDigital Input/OutputVIHVILVOHVOLInput leakagePower-Supply RequirementsAVDDDVDDIOVDDAVDD current (IAVDD)DVDD current (IDVDD)IOVDD current (IIOVDD)Power dissipationTemperature RangeSpecifiedOperatingStorageThermal Resistance, qJA qJCPowerPAD soldered to PCB with 2oz.trace and copper pad.−40−40−60250.5+85+105+150°C°C°C°C/W°C/WREFEN = lowREFEN = highIOVDD = 3VAVDD = 5V, DVDD = 3V, IOVDD = 3V,REFEN = highPD = low, CLK disabled4.752.72.71108527351555.253.35.25135105355645VVVmAmAmAmAmWmWIOH = 50µAIOL = 50µADGND < VDIGIN < IOVDD0.7 IOVDDDGND0.8 IOVDD0.2 IOVDD±10IOVDD0.3 IOVDDVVVVµA1fCLK = 40MHz45405055MHz%Internal reference (REFEN = low)Internal reference (REFEN = low)TEST CONDITIONSMIN2.53.750.752.3TYP3.04.01.02.55015MAX3.24.251.252.8UNITVVVVppm/°Cms(1)The specification limits for VREF, VREFP, VREFN, and VMID apply when using the internal or an external reference. The internal referencevoltages are bounded by the limits shown. When using an external reference, the limits indicate the allowable voltages that can be applied to thereference pins.5http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007DEFINITIONSAbsolute Input VoltageAbsolute input voltage, given in volts, is the voltage of eachanalog input (AINN or AINP) with respect to AGND.Offset ErrorOffset Error, given in % of FSR, is the output reading whenthe differential input is zero.Aperture DelayAperture delay is the delay between the rising edge of CLKand the sampling of the input signal.Offset Error DriftOffset error drift, given in ppm of FSR/_C, is the drift overtemperature of the offset error. The offset error is specifiedas the larger of the drift from ambient (TA = 25_C) to theminimum or maximum operating temperatures.Common-Mode Input VoltageCommon-mode input voltage (VCM) is the average voltageof the analog inputs:Signal-to-Noise Ratio (SNR)SNR, given in dB, is the ratio of the rms value of the inputsignal to the sum of all the frequency components belowfCLK/2 (the Nyquist frequency) excluding the first sixharmonics of the input signal and the dc component.(AINP)AINN)2Differential Input VoltageDifferential input voltage (VIN) is the voltage differencebetween the analog inputs: (AINP−AINN).Signal-to-Noise and Distortion (SINAD)SINAD, given in dB, is the ratio of the rms value of the inputsignal to the sum of all the frequency components belowfCLK/2 (the Nyquist frequency) including the harmonics ofthe input signal but excluding the dc component.Differential Nonlinearity (DNL)DNL, given in least-significant bits (LSB) of the outputcode, is the maximum deviation of the output code stepsizes from the ideal value of 1LSB.Spurious Free Dynamic Range (SFDR)SFDR, given in dB, is the difference between the rmsamplitude of the input signal to the rms amplitude of thepeak spurious signal.Full-Scale Range (FSR)FSR is the difference between the maximum and minimummeasurable input signals. For the ADS1625, FSR = 2 × 1.467VREF.Total Harmonic Distortion (THD)THD, given in dB, is the ratio of the sum of the rms valueof the first six harmonics of the input signal to the rms valueof the input signal.Gain ErrorGain error, given in %, is the error of the full-scale inputsignal with respect to the ideal value.Gain Error DriftGain error drift, given in ppm/_C, is the drift overtemperature of the gain error. The gain error is specified asthe larger of the drift from ambient (TA = 25_C) to theminimum or maximum operating temperatures.Integral Nonlinearity (INL)INL, given in least significant bits (LSB) of the output code,is the maximum deviation of the output codes from a best-fit line.Intermodulation Distortion (IMD)IMD, given in dB, is measured while applying two inputsignals of the same magnitude, but with slightly differentfrequencies. It is calculated as the difference between therms amplitude of the input signal to the rms amplitude ofthe peak spurious signal.6http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007PIN ASSIGNMENTSVREFNVREFNVREFPVREFPIOVDDDGNDDGNDAGNDAGNDDVDDAVDDVCAPVMIDCLKNC5064AGND1AVDD2AGND3AINN4AINP5636261605958575655545352514948FIFO_LEV[2](ADS1626Only)47FIFO_LEV[1](ADS1626Only)46FIFO_LEV[0](ADS1626Only)45NC44DOUT[17]43DOUT[16]42DOUT[15]NC41DOUT[14]40DOUT[13]39DOUT[12]38DOUT[11]37DOUT[10]36DOUT[9]35DOUT[8]34DOUT[7]33DOUT[6]17PD18DVDD19DGND20RESET21CS2223RDOTR24DRDY25DGND26DVDD27DOUT[0]28DOUT[1]29DOUT[2]30DOUT[3]31DOUT[4]32DOUT[5]ADS1625ADS1626TQFP PACKAGE(TOP VIEW)AGND6AVDD7RBIAS8AGND9AVDD10AGND11AVDD12REFEN13IOVDD14DGND15NC16PowerPADTMTerminal FunctionsTERMINALNAMEAGNDAVDDAINNAINPRBIASREFENNCPDDVDDDGNDRESETCSRDOTRDRDYDOUT [17:0]FIFO_LEV[2:0]IOVDDCLKVCAPVREFNVMIDVREFPNO.1, 3, 6, 9, 11, 55, 572, 7, 10, 12, 584581316, 45, 49, 501718, 26, 5215, 19, 25, 51, 54202122232427−4446−4814, 53565960, 616263, 64Digital input: active lowDigitalDigitalDigital input: active lowDigital input: active lowDigital input: active lowDigital outputDigital output: active lowDigital outputDigital inputDigitalDigital inputAnalogAnalogAnalogAnalogTYPEAnalogAnalogAnalog inputAnalog inputAnalogDigital input: active lowAnalog groundAnalog supplyNegative analog inputPositive analog inputTerminal for external analog bias setting resistorInternal reference enable. Internal pull-down resistor of 170kΩ to DGND.Must be left unconnectedPower down all circuitry. Internal pull-up resistor of 170kΩ to DGND.Digital supplyDigital groundReset digital filterChip selectRead enableActive when analog inputs are out of rangeData ready on falling edgeData output. DOUT[17] is the MSB and DOUT[0] is the LSB.FIFO level (for the ADS1626 only). FIFO_LEV[2] is MSB.NOTE: These terminals must be left unconnected on the ADS1625.Digital I/O supplyClock inputTerminal for external bypass capacitor connection to internal bias voltageNegative reference voltageMidpoint voltagePositive reference voltageDESCRIPTION 7http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007PARAMETER MEASUREMENT INFORMATIONt1CLKt2t3DRDYt5DOUT[17:0]DataNt6DataN+1DataN+2t4t4t2NOTE:CSandRDtiedlow.Figure 1. Data Retrieval Timing (ADS1625, ADS1626 with FIFO Disabled)RD,CSt7DOUT[17:0]t8Figure 2. DOUT Inactive/Active Timing (ADS1625, ADS1626 with FIFO Disabled)TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2 SYMBOLt11/t1t2t3t4t5t6t7t8DESCRIPTIONCLK period (1/fCLK)fCLKCLK pulse width, high or lowRising edge of CLK to DRDY lowDRDY pulse width high or lowFalling edge of DRDY to data invalidFalling edge of DRDY to data validRising edge of RD and/or CS inactive (high) to DOUT high impedanceFalling edge of RD and/or CS active (low) to DOUT active.MIN201101016 t110151515TYP2540MAX100050UNITnsMHznsnsnsnsnsnsnsNOTE:DOUT[17:0] and DRDY load = 10pF.8http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007CLKt11RESETt9t10DRDYt3DOUT[17:0]SettledDatat12NOTE:CSandRDtiedlow.Figure 3. Reset Timing (ADS1625, ADS1626 with FIFO Disabled)TIMING REQUIREMENTS FOR FIGURE 3 SYMBOLt3t9t10t11t12DESCRIPTIONRising edge of CLK to DRDY lowRESET pulse widthDelay from RESET active (low) to DRDY forced high and DOUT forced lowRESET rising edge to falling edge of CLKDelay from DOUT active to valid DOUT (settling to 0.001%)−54650910MINTYP10MAXUNITnsnsnsnsDRDYCyclesNOTE:DOUT[17:0] and DRDY load = 10pF.9http://oneic.com/ADS1625ADS1626www.ti.comSBAS280E − JUNE 2003 − REVISED MAY 2007t1CLKt13DRDYt16CS(1)t17RDDOUT[17:0]t18D1t19D2DL(2)t21t20t2t14t15t2(1)CSmaybetiedlow.(2)Thenumberofdatareadings(DL)issetbytheFIFOlevel.Figure 4. Data Retrieval Timing (ADS1626 with FIFO Enabled)RD,CSt7DOUT[17:0]t8Figure 5. DOUT Inactive/Active Timing (ADS1626 with FIFO Enabled)TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5 SYMBOLt1t2t7t8t13t14t15t16t17t18t19t20t21DESCRIPTIONCLK period (1/fCLK)CLK pulse width, high or lowRising edge of RD and/or CS inactive (high) to DOUT high impedanceFalling edge of RD and/or CS active (low) to DOUT active.Rising edge of CLK to DRDY highDRDY periodDRDY positive pulse widthRD high hold time after DRDY goes lowCS low before RD goes lowRD negative pulse widthRD positive pulse widthRD high before DRDY togglesRD high before CS goes high00101020MIN2010771232 ×FIFO Level(1)11515TYP25MAX1000UNITnsnsnsnsnsCLKCyclesCLKCyclesnsnsnsnsCLKCyclesnsNOTE:DOUT[17:0] and DRDY load = 10pF.(1)See FIFO section for more details.10http://oneic.com/
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ADS1626IPAPT