Revised September 2000
74F160A • 74F162A
Synchronous Presettable BCD Decade Counter
General Description
The 74F160A and 74F162A are high-speed synchronousdecade counters operating in the BCD (8421) sequence.They are synchronously presettable for applications in pro-grammable dividers. There are two types of Count Enableinputs plus a Terminal Count output for versatility in formingsynchronous multistage counters. The F160A has an asyn-chronous Master Reset input that overrides all other inputsand forces the outputs LOW. The F162A has a Synchro-nous Reset input that overrides counting and parallel load-ing and allows all outputs to be simultaneously reset on therising edge of the clock. The F160A and F162A are highspeed versions of the F160 and F162.
Features
sSynchronous counting and loadingsHigh-speed synchronous expansionsTypical count rate of 120 MHz
Ordering Code:
Order Number74F160ASC 74F160ASJ 74F160APC74F162ASC 74F162APC
Package Number
M16AM16DN16EM16AN16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F160A74F162A
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74F160A • 74F162ALogic Symbols
74F160AIEEE/IEC
74F162A
74F160A
74F162A
Unit Loading/Fan Out
Pin NamesCEPCETCP
Description
Count Enable Parallel InputCount Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
U.L.
Input IIH/IIL
HIGH/LOWOutput IOH/IOL1.0/1.01.0/2.01.0/1.01.0/1.01.0/2.01.0/1.01.0/2.050/33.350/33.3
20 µA/−0.6 mA20 µA/−1.2 mA20 µA/−0.6 mA20 µA/−0.6 mA20 µA/−1.2 mA20 µA/−0.6 mA20 µA/−1.2 mA
MR (74F160A)Asynchronous Master Reset Input (Active LOW)SR (74F162A)Synchronous Reset Input (Active LOW)P0–P3PEQ0–Q3TC
Parallel Data Inputs
Parallel Enable Input (Active LOW)Flip-Flop OutputsTerminal Count Output
−1 mA/20 mA−1 mA/20 mA
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74F160A • 74F162AFunctional Description
The 74F160A and 74F162A count modulo-10 in the BCD(8421) sequence. From state 9 (HLLH) they increment tostate 0 (LLLL). The clock inputs of all flip-flops are driven inparallel through a clock buffer. Thus all changes of the Qoutputs (except due to Master Reset of the (F160A) occuras a result of, and synchronous with, the LOW-to-HIGHtransition of the CP input signal. The circuits have four fun-damental modes of operation, in order of precedence:asynchronous reset (F160A), synchronous reset (F162A),parallel load, count-up and hold. Five control inputs—Mas-ter Reset (MR, F160A), Synchronous Reset (SR, F162A),Parallel Enable (PE), Count Enable Parallel (CEP) andCount Enable Trickle (CET)—determine the mode of oper-ation, as shown in the Mode Select Table. A LOW signal onMR overrides all other inputs and asynchronously forces alloutputs LOW. A LOW signal on SR overrides counting andparallel loading and allows all outputs to go LOW on thenext rising edge of CP. A LOW signal on PE overridescounting and allows information on the Parallel Data (Pn)inputs to be loaded into the flip-flops on the next risingedge of CP. With PE and MR (F160A) or SR (F162A)HIGH, CEP and CET permit counting when both are HIGH.Conversely, a LOW signal on either CEP or CET inhibitscounting.
The F160A and F162A use D-type edge-triggered flip-flopsand changing the SR, PE, CEP and CET inputs when theCP is in either state does not cause errors, provided thatthe recommended setup and hold times, with respect to therising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET isHIGH and counter is in state 9. To implement synchronousmultistage counters, the TC outputs can be used with theCEP and CET inputs in two different ways. Please refer tothe F568 data sheet. The TC output is subject to decodingspikes due to internal race conditions and is therefore notrecommended for use as a clock or asynchronous reset forflip-flops, counters or registers. In the F160A and F162Adecade counters, the TC output is fully decoded and canonly be HIGH in state 9. If a decade counter is preset to anillegal state, or assumes an illegal state when power isapplied, it will return to the normal sequence within twocounts, as shown in the State Diagram.Logic Equations:
Count Enable = CEP × CET × PE
TC = Q0 × Q 1× Q 2 × Q3 × CET
Mode Select Table
*SRLHHHH
PEXLHHH
CETCEPXXHLX
XXHXL
Action on the RisingClock Edge ()
Reset (Clear)Load (Pn → Qn)Count (Increment)No Change (Hold)No Change (Hold)
State Diagram
*For 74’F162A only
H = HIGH Voltage LevelL = LOW Voltage LevelX = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F160A • 74F162AAbsolute Maximum Ratings(Note 1)
Storage Temperature
Ambient Temperature under BiasJunction Temperature under BiasVCC Pin Potential to Ground PinInput Voltage (Note 2)Input Current (Note 2)Voltage Applied to Outputin HIGH State (with VCC = 0V)Standard Output3-STATE OutputCurrent Applied to Outputin LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated IOL (mA)
4000V
−65°C to +150°C−55°C to +125°C−55°C to +150°C−0.5V to +7.0V−0.5V to +7.0V−30 mA to +5.0 mA
Recommended OperatingConditions
Free Air Ambient TemperatureSupply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to VCC−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the devicemay be damaged or have its useful life impaired. Functional operationunder these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
SymbolVIHVILVCDVOHVOLIIHIBVIICEXVIDIODIILIOSICC
Parameter
Input HIGH VoltageInput LOW VoltageInput Clamp Diode VoltageOutput HIGHVoltageOutput LOWVoltageInput HIGHCurrent
InputHIGHCurrentBreakdownTestOutput HIGHLeakageCurrentInputLeakageTest
OutputLeakageCircuitCurrentInput LOWCurrent
Output Short-Circuit CurrentPower Supply Current
−60
37
4.75
3.75−0.6−1.2−15055
10%VCC5%VCC10% VCC
2.52.7
0.55.07.050
Min2.0
0.8−1.2
Typ
Max
UnitsVVVVVµAµAµAVµAmAmAmAmA
MinMinMinMaxMaxMax0.00.0MaxMaxMaxMaxVCC
Conditions
Recognized as a HIGH SignalRecognized as a LOW SignalIIN = −18 mAIOH = −1 mAIOH = −1 mAIOL = 20 mAVIN = 2.7VVIN = 7.0VVOUT = VCCIID = 1.9 µA
All Other Pins GroundedVIOD = 150 mV
All Other Pins Grounded
VIN = 0.5V (CP, CEP,Pn, MR (F160A))VIN = 0.5V (CET, SR (F162A), PE)VOUT = 0VVO = HIGH
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74F160A • 74F162AAC Electrical Characteristics
TA = +25°C
Symbol
Parameter
Min
fMAXtPLHtPHLtPLHtPHLtPLHtPHLtPLHtPHLtPHLtPHL
Maximum Count FrequencyPropagation Delay, CountCP to Qn (PE Input HIGH)Propagation Delay, LoadCP to Qn (PE Input LOW)Propagation DelayCP to TC
Propagation DelayCET to TCPropagation DelayMR to Qn (74F160A)Propagation DelayMR to TC (74F160A)
903.53.54.04.05.05.02.52.55.54.5
VCC = +5.0VCL = 50 pF
Typ1205.57.56.06.010.010.04.54.59.08.0
7.510.08.58.514.014.07.57.512.010.5Max
TA = −55°C to +125°C
VCC = +5.0VCL = 50 pFMin753.53.54.04.05.05.02.52.55.54.5
9.011.510.010.016.515.59.09.014.012.5Max
TA = 0°C to +70°CVCC = +5.0VCL = 50 pFMin803.53.54.04.05.05.02.52.55.54.5
8.511.09.59.515.015.08.58.513.011.5Max
MHznsnsnsnsnsnsUnits
AC Operating Requirements
TA = +25°C
SymboltS(H)tS(L)tS(H)tS(L)tH(H)tH(L)tS(H)tS(L)tH(H)tH(L)tS(H)tS(L)tH(H)tH(L)tW(H)tW(L)tW(H)tW(L)tW(L)tREC
Parameter
Setup Time, HIGH or LOWPn to CP (74F160A)Setup Time, HIGH or LOWPn to CP (74F162A)Hold Time, HIGH or LOWPn to CP
Setup Time, HIGH or LOWPE or SR to CP
Hold Time, HIGH or LOWPE or SR to CP
Setup Time, HIGH or LOWCEP or CET to CPHold Time, HIGH or LOWCEP or CET to CPClock Pulse Width (Load)HIGH or LOW
Clock Pulse Width (Count)HIGH or LOWMR Pulse Width, LOW(74F160A)Recovery TimeMR to CP (74F160A)
VCC = +5.0VMin4.05.05.05.02.02.011.08.52.0011.05.0005.05.04.06.05.06.0
2.52.513.510.52.0013.06.0005.05.05.08.05.06.0
Max
TA = −55°C to +125°C
VCC = +5.0VMin5.55.5
Max
TA = 0°C to +70°CVCC = +5.0VMin4.05.05.05.02.02.011.59.52.0011.55.0005.05.04.07.05.06.0
nsnsnsnsnsns
Max
nsUnits
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74F160A • 74F162APhysical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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74F160A • 74F162APhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74F160A • 74F162A Synchronous Presettable BCD Decade CounterPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.www.fairchildsemi.com
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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
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