元器件交易网www.cecb2b.com SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998DEPIC™ (Enhanced-Performance ImplantedDDDDDDCMOS) Submicron ProcessTypical VOLP (Output Ground Bounce)< 0.8 V at VCC = 3.3 V, TA = 25°CTypical VOHV (Output VOH Undershoot)> 2 V at VCC = 3.3 V, TA = 25°CInputs Accept Voltages to 5.5 VESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA PerJESD 17Package Options Include PlasticSmall-Outline (D), Shrink Small-Outline(DB), Thin Shrink Small-Outline (PW)Packages, Ceramic Flat (W), Chip Carriers(FK), and DIPs (J)SN54LVC02A...J OR W PACKAGESN74LVC02A...D, DB, OR PW PACKAGE(TOP VIEW)1Y1A1B2Y2A2BGND1234567141312111098VCC4Y4B4A3Y3B3ASN54LVC02A...FK PACKAGE(TOP VIEW)1A1YNCVCC3descriptionThe SN54LVC02A quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V VCCoperation and the SN74LVC02A quadruple2-input positive-NOR gate is designed for 1.65-Vto 3.6-V VCC operation.The ’LVC02A devices perform the Booleanfunction Y = A + B or Y = A • B in positive logic.Inputs can be driven from either 3.3-V or 5-Vdevices. This feature allows the use of thesedevices as translators in a mixed 3.3-V/5-Vsystem environment.The SN54LVC02A is characterized for operationover the full military temperature range of –55°Cto 125°C. The SN74LVC02A is characterized foroperation from –40°C to 85°C.FUNCTION TABLE(each gate)INPUTSAHXLBXHLOUTPUTYLLH1BNC2YNC2A45678212019181716154Y4BNC4ANC3Y14910111213NC – No internal connectionPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.EPIC is a trademark of Texas Instruments Incorporated.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1998, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•2BGNDNC3A3B1元器件交易网www.cecb2b.comSCAS280I – JANUARY 1993 – REVISED OCTOBER 1998SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES logic symbol†1A1B2A2B3A3B4A4B2356891112134Y103Y42Y≥ 111Y †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.Pin numbers shown are for the D, DB, J, PW, and W packages.logic diagram, each gate (positive logic)ABYabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡Supply-voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 VInput-voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 VOutput-voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 VInput clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAOutput clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAContinuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mAPackage thermal impedance, θJA (see Note 3):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/WDB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/WPW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/WStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The value of VCC is provided in the recommended operating conditions table.3.The package thermal impedance is calculated in accordance with JESD 51.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998recommended operating conditions (see Note 4)SN54LVC02AMINVCCSupplyvoltageSupply voltageOperatingData retention onlyVCC = 1.65 V to 1.95 VVCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 VVCC = 1.65 V to 1.95 VVILVIVOLow-level input voltageInput voltageOutput voltageVCC = 1.65 VVCC = 2.3 VVCC = 2.7 VVCC = 3 VVCC = 1.65 VVCC = 2.3 VVCC = 2.7 VVCC = 3 V1224–12–24VCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 V00221.5MAX3.6SN74LVC02AMIN1.651.50.65 ×VCC1.720.35 ×VCC0.70.85.5VCC000.85.5VCC–4–8–12–24481224mAVVVVMAX3.6UNITVVIHHigh-level input voltageIOHHighleveloutputcurrentHigh-level output currentmAIOLLowleveloutputcurrentLow-level output currentTAOperating free-air temperature–55125–4085°CNOTE 4:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCAS280I – JANUARY 1993 – REVISED OCTOBER 1998SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTESTCONDITIONSTEST CONDITIONSIOH = –100 =100µAIOH = –4 mAIOH = –8 mAIOH = –12 mA=12mAIOH = –24 mA=100µAIOL = 100 VOLIOL = 4 mAIOL = 8 mAIOL = 12 mAIOL = 24 mAIIICC∆ICCCiVI = 5.5 V or GNDVI = VCC or GND,IO = 0One input at VCC – 0.6 V,Other inputs at VCC or GNDVCC1.65 V to 3.6 V2.7 V to 3.6 V1.65 V2.3 V2.7 V3 V3 V1.65 V to 3.6 V2.7 V to 3.6 V1.65 V2.3 V2.7 V3 V3.6 V3.6 V2.7 V to 3.6 V3.3 V50.40.55±51050050.20.450.70.40.55±510500µAµAµApFV2.22.42.2VCC–0.21.21.72.22.42.20.2VSN54LVC02AMINTYP†MAXSN74LVC02AMINTYP†MAXVCC–0.2UNITVOHVI = VCC or GND†All typical values are at VCC = 3.3 V, TA = 25°C.switching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figure 3)SN54LVC02APARAMETERFROM(INPUT)A or BTO(OUTPUT)YVCC = 2.7 VMINtpdMAX5.4VCC = 3.3 V± 0.3 VMIN1MAX4.4nsUNITswitching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figures 1 through 3)SN74LVC02APARAMETERFROM(INPUT)A or BTO(OUTPUT)YVCC = 1.8 VTYPtpdtsk(o)‡‡Skew between any two outputs of the same package switching in the same direction13.4VCC = 2.5 V± 0.2 VMIN1MAX7.4VCC = 2.7 VMINMAX5.4VCC = 3.3 V± 0.3 VMIN1MAX4.41nsnsUNIToperating characteristics, TA = 25°CPARAMETERCpdPower dissipation capacitance per gateTESTCONDITIONSf = 10 MHzVCC = 1.8 VTYP7.5VCC = 2.5 VTYP8.5VCC = 3.3 VTYP9.5UNITpF4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998PARAMETER MEASUREMENT INFORMATIONVCC = 1.8 V ± 0.15 V1 kΩS12 × VCCOpenGND1 kΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCOpenFrom OutputUnder TestCL = 30 pF(see Note A)LOAD CIRCUITVCC0 VtsuDataInputVCC/2thVCCVCC/20 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVCCInputVCC/2tPLHOutputVCC/2VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVCC/20 VtPHLVOHVCC/2VOLOutputWaveform 2S1 at Open(see Note B)OutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHtwInputVCC/2VOLTAGE WAVEFORMSPULSE DURATIONVCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + 0.15 VVOLtPHZVCC/2VOHVOH – 0.15 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESVCC/2VCC0 VTimingInputVCC/2NOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSCAS280I – JANUARY 1993 – REVISED OCTOBER 1998SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES PARAMETER MEASUREMENT INFORMATIONVCC = 2.5 V ± 0.2 V500 ΩS12 × VCCOpenGND500 ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCGND From OutputUnder TestCL = 30 pF(see Note A)LOAD CIRCUITVCC0 VtsuDataInputVCC/2thVCCVCC/20 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVCCInputVCC/2tPLHOutputVCC/2VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVCC/20 VtPHLVOHVCC/2VOLOutputWaveform 2S1 at GND(see Note B)OutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHtwInputVCC/2VOLTAGE WAVEFORMSPULSE DURATIONVCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + 0.15 VVOLtPHZVCC/2VOHVOH – 0.15 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESVCC/2VCC0 VTimingInputVCC/2NOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 2. Load Circuit and Voltage Waveforms6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54LVC02A, SN74LVC02AQUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998PARAMETER MEASUREMENT INFORMATIONVCC = 2.7 V AND 3.3 V ± 0.3 V6 VFrom OutputUnder TestCL = 50 pF(see Note A)500 ΩS1OpenGND500 ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open6 VGNDLOAD CIRCUITtw2.7 VTimingInputtsuDataInput1.5 V2.7 V1.5 V0 Vth2.7 V1.5 V0 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESInput1.5 V1.5 V0 VVOLTAGE WAVEFORMSPULSE DURATIONOutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 6 V(see Note B)OutputWaveform 2S1 at GND(see Note B)tPZH2.7 V1.5 V1.5 V0 VtPLZ3 V1.5 VtPHZVOH – 0.3 VVOL + 0.3 VVOL2.7 VInputtPLH1.5 V1.5 V0 VtPHLVOHOutput1.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES1.5 VVOLVOH0 V1.5 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 3. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.com
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