SCAN COMPRESSION ARCHITECTURE FOR A DESIGN FOR TES

专利名称：SCAN COMPRESSION ARCHITECTURE FOR A

DESIGN FOR TESTABILITY COMPILER USEDIN SYSTEM-ON-CHIP SOFTWARE DESIGNTOOLS

发明人：Marco Casarsa申请号：US11744631申请日：20070504

公开号：US20070283200A1公开日：20071206

专利附图：

摘要：A scan compression architecture for a design for testability compiler used in

system-on-chip software design tools includes a first scan architecture including a firstscan compressor/decompressor configuration connected to a first predetermined set ofpins, and a second scan architecture including a second scan compressor/decompressorconfiguration connected to a subset of the pins. The first scan architecture is selectivelyenabled for executing a scan test with a low time. The second scan architecture is forexecuting a scan test with high parallelism.

申请人：Marco Casarsa

地址：Vaprio d'Adda (MI) IT

国籍：IT

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