专利名称：Scan testing integrated circuits发明人：Ganapathy, Gopi,Thaden, Robert,Horne,
Steve
申请号：EP93307968.3申请日：19931007公开号：EP0600594A1公开日：19940608
专利附图：
摘要：A test circuit and test technique for scan testing integrated circuits is disclosed.The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistorsthan conventional scan latches. The testing technique utilizes the clock input to the
latches in the ICs for propagating data through the latches. The test circuit and testtechniques are highly advantageous for use with microprocessors and particularly RISCmicroprocessors. The test technique includes coupling a drive 1 or drive 0 element to alogic element coupled to a general latch. The drive 1 or drive 0 scan element allows thegeneral latch to be clocked by a clock signal such as a φ1 clock signal or φ2 clock signal.
申请人：ADVANCED MICRO DEVICES, INC.
地址：901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088 US
国籍：US
代理机构：BROOKES & MARTIN
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