IS41LV16100A
1M x 16 (16-MBIT) DYNAMIC RAMWITH EDO PAGE MODE
FEATURES
•TTL compatible inputs and outputs; tristate I/O•Refresh Interval:
—Auto refresh Mode: 1,024 cycles /16 ms—RAS-Only, CAS-before-RAS (CBR), and Hidden•JEDEC standard pinout•Single power supply:
—3.3V ± 10% (IS41LV16100A)
•Byte Write and Byte Read operation via two CAS•Industrial Temperature Range: -40oC to +85oC•Lead-free available
ISSI
MARCH 2005
®
DESCRIPTION
The ISSI IS41LV16100A is 1,048,576 x 16-bit high-perfor-mance CMOS Dynamic Random Access Memories. Thesedevices offer an accelerated cycle access called EDOPage Mode. EDO Page Mode allows 1,024 random ac-cesses within a single row with access cycle time as shortas 20 ns per 16-bit word.
These features make the IS41LV16100A ideally suited forhigh-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheralapplications.
The IS41LV16100A is packaged in a 42-pin 400-mil SOJand 400-mil 50- (44-) pin TSOP (Type II).
KEY TIMING PARAMETERS
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)42-Pin SOJParameterMax. RAS Access Time (tRAC)Max. CAS Access Time (tCAC)Max. Column Address Access Time (tAA)VDDI/O0I/O1I/O2I/O3VDDI/O4I/O5I/O6I/O7NC NCNCWERASNCNCA0A1A2A3VDD12131415161718192021223332313029282726252423NC LCASUCASOEA9A8 A7 A6 A5 A4 GND12345678910114443424140393837363534GNDI/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8NC-505014253085-6060153040110UnitnsnsnsnsnsVDDI/O0I/O1I/O2I/O3VDDI/O4I/O5I/O6I/O7NCNCWERASNCNCA0A1A2A3VDD123456789101112131415161718192021424140393837363534333231302928272625242322GNDI/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCASUCASOEA9A8 A7 A6 A5 A4 GNDMin. EDO Page Mode Cycle Time (tPC)Min. Read/Write Cycle Time (tRC)PIN DESCRIPTIONS
A0-A9I/O0-15WEOERASUCASLCASVDDGNDNC
Address InputsData Inputs/OutputsWrite EnableOutput EnableRow Address Strobe
Upper Column Address StrobeLower Column Address StrobePowerGroundNo Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. B03/02/05
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IS41LV16100A
FUNCTIONAL BLOCK DIAGRAM
ISSI
®
OEWELCASUCASCAS CLOCKGENERATORWECONTROLLOGICSOE CONTROLLOGICOECASWERASRAS CLOCKGENERATORDATA I/O BUSCOLUMN DECODERSSENSE AMPLIFIERSREFRESH COUNTERDATA I/O BUFFERSROW DECODERRASI/O0-I/O15MEMORY ARRAY1,048,576 x 16A0-A9ADDRESSBUFFERS2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
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IS41LV16100A
TRUTH TABLE
FunctionStandbyRead: WordRead: Lower ByteRead: Upper ByteWrite: Word (Early Write)Write: Lower Byte (Early Write)Write: Upper Byte (Early Write)Read-Write(1,2)EDO Page-Mode Read(2)1st Cycle:2nd Cycle:Any Cycle:EDO Page-Mode Write(1)1st Cycle:2nd Cycle:EDO Page-Mode(1,2)Read-WriteHidden RefreshRAS-Only RefreshCBR Refresh(4)1st Cycle:2nd Cycle:Read(2)Write(1,3)RASHLLLLLLLLLLLLLLL→H→LL→H→LLH→LLCASUCASHLLHLLHLH→LH→LL→HH→LH→LH→LH→LLLHLHLHLLHLLH→LH→LL→HH→LH→LH→LH→LLLHLWEXHHHLLLH→LHHHLLH→LH→LHLXXOEXLLLXXXL→HLLLXXL→HL→HLXXXAddress tR/tCXROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLROW/COLNA/COLNA/NAROW/COLNA/COLROW/COLNA/COLROW/COLROW/COLROW/NAXI/OISSI
High-ZDOUT®
Lower Byte, DOUTUpper Byte, High-ZLower Byte, High-ZUpper Byte, DOUTDINLower Byte, DINUpper Byte, High-ZLower Byte, High-ZUpper Byte, DINDOUT, DINDOUTDOUTDOUTDINDINDOUT, DINDOUT, DINDOUTDOUTHigh-ZHigh-ZNotes:
1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).3.EARLY WRITE only.
4.At least one of the two CAS signals must be active (LCAS or UCAS).
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IS41LV16100A
Functional Description
The IS41LV16100A is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ orWRITE cycles, each bit is uniquely addressed through the16 address bits. These are entered ten bits (A0-A9) at time.The row address is latched by the Row Address Strobe(RAS). The column address is latched by the ColumnAddress Strobe (CAS). RAS is used to latch the first nine bitsand CAS is used to latch the latter nine bits.The IS41LV16100A has two CAS controls, LCAS andUCAS. The LCAS and UCAS inputs internally generates aCAS signal functioning in an identical manner to the single CASinput on the other 1M x 16 DRAMs. The key difference is thateach CAS controls its corresponding I/O tristate logic (inconjunction with OE and WE and RAS). LCAS controls I/O0through I/O7 and UCAS controls I/O8 through I/O15.The IS41LV16100A CAS function is determined by the firstCAS (LCAS or UCAS) transitioning LOW and the lasttransitioning back HIGH. The two CAS controls give theIS41LV16100A both BYTE READ and BYTE WRITE cyclecapabilities.
ISSI
Auto Refresh Cycle
®
To retain data, 1,024 refresh cycles are required in each16 ms period. There are two ways to refresh the memory.1.By clocking each of the 1,024 row addresses (A0 through A9)with RAS at least once every 128 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row.2.Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS,while holding CAS LOW. In CAS-before-RAS refreshcycle, an internal 9-bit counter provides the row ad-dresses and the external address inputs are ignored.CAS-before-RAS is a refresh-only mode and no dataaccess or device selection is allowed. Thus, the outputremains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns withina selected row to be randomly accessed at a high data rate.In EDO page mode read cycle, the data-out is held to thenext CAS cycle’s falling edge, instead of the rising edge.For this reason, the valid data output time in EDO pagemode is extended compared with the fast page mode. Inthe fast page mode, the valid data output time becomesshorter as the CAS cycle time becomes shorter. There-fore, in EDO page mode, the timing margin in read cycleis larger than that of the fast page mode even if the CAScycle time becomes shorter.
In EDO page mode, due to the extended data function, theCAS cycle time can be shorter than in the fast page modeif the timing margin is the same.
The EDO page mode allows both read and write opera-tions during one RAS cycle, but the performance isequivalent to that of the fast page mode in that case.Power-On
After application of the VDD supply, an initial pause of200 µs is required followed by a minimum of eightinitialization cycles (any combination of cycles contain-ing a RAS signal).
During power-on, it is recommended that RAS track withVDD or be held at a valid VIH to avoid current surges.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it isterminated by returning both RAS and CAS HIGH. Toensures proper device operation and data integrity anymemory cycle, once initiated, must not be ended oraborted before the minimum tRAS time has expired. A newcycle must not be initiated until the minimum prechargetime tRP, tCP has elapsed.Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,whichever occurs last, while holding WE HIGH. The columnaddress must be held for a minimum time specified by tAR.Data Out becomes valid only when tRAC, tAA, tCAC and tOEAare all satisfied. As a result, the access time is dependenton the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,whichever occurs last. The input data must be valid at orbefore the falling edge of CAS or WE, whichever occurs first.
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IS41LV16100A
ABSOLUTE MAXIMUM RATINGS(1)
SymbolVTVDDIOUTPDTATSTG
Parameters
Voltage on Any Pin Relative to GNDSupply VoltageOutput CurrentPower Dissipation
Commercial Operation TemperatureIndustrial Operation TemperatureStorage Temperature
3.3V3.3V
Rating–0.5 to +4.6–0.5 to +4.6
5010 to +70-40 to +85–55 to +125
UnitVVmAW°C°C°C
ISSI
®
Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
SymbolVDDVIHVILTA
ParameterSupply VoltageInput High VoltageInput Low Voltage
Commercial Ambient TemperatureIndustrial Ambient Temperature
3.3V3.3V3.3V
Min.3.02.0–0.30–40
Typ.3.3————
Max.3.6VDD + 0.30.87085
UnitVVV°C°C
CAPACITANCE(1,2)
SymbolCIN1CIN2CIO
Parameter
Input Capacitance: A0-A9
Input Capacitance: RAS, UCAS, LCAS, WE, OEData Input/Output Capacitance: I/O0-I/O15
Max.577
UnitpFpFpF
Notes:
1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: TA = 25°C, f = 1 MHz.
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IS41LV16100A
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)SymbolIILIIOVOHVOLICC1ICC2ICC3
Parameter
Input Leakage CurrentOutput Leakage CurrentOutput High Voltage LevelOutput Low Voltage LevelStandby Current: TTLStandby Current: CMOSOperating Current:
Random Read/Write(2,3,4)
Average Power Supply CurrentOperating Current:EDO Page Mode(2,3,4)
Average Power Supply CurrentRefresh Current:RAS-Only(2,3)
Average Power Supply CurrentRefresh Current:CBR(2,3,5)
Average Power Supply CurrentTest Condition
Any input 0V ≤ VIN ≤ VDD
Other inputs not under test = 0VOutput is disabled (Hi-Z)0V ≤ VOUT ≤ VDDIOH = –2.0 mA (3.3V)IOL = 2.0 mA (3.3V)RAS, LCAS, UCAS ≥ VIH
Commercial3.3VIndustrial3.3V
3.3V-50-60-50-60-50-60-50-60Speed
Min.–10–102.4————————————
ISSI
Max.1010—0.4342180170180170180170180170
µAµAVV
®
Unit
mAmAmAmA
RAS, LCAS, UCAS ≥ VDD – 0.2VRAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)RAS = VIL, LCAS, UCAS,Cycling tPC = tPC (min.)
RAS Cycling, LCAS, UCAS ≥ VIHtRC = tRC (min.)
RAS, LCAS, UCAS CyclingtRC = tRC (min.)
ICC4mA
ICC5mA
ICC6mA
Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.2.Dependent on cycle rates.
3.Specified values are obtained with minimum cycle time and the output open.4.Column-address is changed once each EDO page cycle.5.Enables on-chip refresh and address counters.
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IS41LV16100A
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
SymboltRCtRACtCACtAAtRAStRPtCAStCPtCSHtRCDtASRtRAHtASCtCAHtARtRADtRALtRPCtRSHtCLZtCRPtODtOE/tOEAtOEHCtOEPtOEStRCStRRHtRCHtWCHtWCR
Parameter
Random READ or WRITE Cycle TimeAccess Time from RAS(6, 7)Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)RAS Pulse WidthRAS Precharge TimeCAS Pulse Width(26)CAS Precharge Time(9, 25)CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)Row-Address Setup TimeRow-Address Hold TimeColumn-Address Setup Time(20)Column-Address Hold Time(20)
Column-Address Hold Time(referenced to RAS)
RAS to Column-Address Delay Time(11)Column-Address to RAS Lead TimeRAS to CAS Precharge TimeRAS Hold Time(27)
CAS to Output in Low-Z(15, 29)CAS to RAS Precharge Time(21)Output Disable Time(19, 28, 29)Output Enable Time(15, 16)
OE HIGH Hold Time from CAS HIGHOE HIGH Pulse Width
OE LOW to CAS HIGH Setup TimeRead Command Setup Time(17, 20)Read Command Hold Time(referenced to RAS)(12)
Read Command Hold Time(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)Write Command Hold Time(referenced to RAS)(17)
Min.85———50308950120808301425514053—15105000840
Max.—50142510K—10K——37—————25—————1214————————
Min.110———604010106020010010401530515053—151050001050
-60Max.—60153010K—10K——45—————30—————1215————————
ISSI
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
®
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IS41LV16100A
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
SymboltWPtWPZtRWLtCWLtWCStDHRtOEHtDStDHtRWCtRWDtCWDtAWDtPCtRASPtCPAtPRWCtCOHtOFFtWHZtCLCHtCSRtCHRtORDtREFtT
Parameter
Write Command Pulse Width(17)
WE Pulse Widths to Disable OutputsWrite Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)Write Command Setup Time(14, 17, 20)Data-in Hold Time (referenced to RAS)OE Hold Time from WE duringREAD-MODIFY-WRITE cycle(18)Data-In Setup Time(15, 22)Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle TimeRAS to WE Delay Time duringREAD-MODIFY-WRITE Cycle(14)CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)EDO Page Mode READ or WRITECycle Time(24)
RAS Pulse Width in EDO Page ModeAccess Time from CAS Precharge(15)EDO Page Mode READ-WRITECycle Time(24)
Data Output Hold after CASLOWOutput Buffer Turn-Off Delay fromCAS or RAS(13,15,19, 29)
Output Disable Delay from WELast CAS going LOW to First CASreturning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)CAS Hold Time (CBR REFRESH)(30, 21)OE Setup Time prior to RAS duringHIDDEN REFRESH CycleAuto Refresh Period (1,024 Cycles)Transition Time (Rise or Fall)(2, 3)
Min.81013803914081106526403050—5653310580—3
Max.——————————————100K30——1210————1650
Min.10101515040150151558540554060—56533105100—3-60Max.——————————————100K35——1515————1650
ISSI
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsns
®
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IS41LV16100A
AC TEST CONDITIONS
Output load:One TTL Load and 50 pF (VDD = 3.3V ±10%)
Input timing reference levels:VIH = 2.0V, VIL = 0.8V (VDD = 3.3V ±10%)Output timing reference levels:VOH = 2.0V, VOL = 0.8V
ISSI
®
Notes:
1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper deviceoperation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2.VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH andVIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3.In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in amonotonic manner.
4.If CAS and RAS = VIH, data output is High-Z.
5.If CAS = VIL, data output may contain data from the last valid READ cycle.6.Measured with a load equivalent to one TTL gate and 50 pF.
7.Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increaseby the amount that tRCD exceeds the value shown.8.Assumes that tRCD ≤ tRCD (MAX).
9.If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the dataoutput buffer, CAS and RAS must be pulsed for tCP.
10.Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11.Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.12.Either tRCH or tRRH must be satisfied for a READ cycle.
13.tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14.tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≤ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≤ tRWD(MIN), tAWD ≤ tAWD (MIN) and tCWD ≤ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read fromthe selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go backto VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.15.Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.17.Write command is defined as WE going low.
18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW andOE is taken back to LOW after tOEH is met.
19.The I/Os are in open during READ cycles once tOD or tOFF occur.20.The first χCAS edge to transition LOW.21.The last χCAS edge to transition HIGH.
22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.
23.Last falling χCAS edge to first rising χCAS edge.
24.Last rising χCAS edge to next cycle’s last rising χCAS edge.25.Last rising χCAS edge to first falling χCAS edge.26.Each χCAS must meet minimum pulse width.27.Last χCAS to go LOW.
28.I/Os controlled, regardless UCAS and LCAS.
29.The 3 ns minimum is a parameter guaranteed by design.30.Enables on-chip refresh and address counters.
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IS41LV16100A
READ CYCLE
ISSI
tRCtRAStRP®
RAStCSHtCRPtRCDtRSHtCAStCLCHtRRHUCAS/LCAStARtRADtASRtRAHtASCtRALtCAHADDRESSWE RowtRCSColumntRCHtAAtRACtCACtCLCtOFF(1)RowI/OOEOpentOEValid DatatODOpentOESUndefinedDon’t CareNote:
1.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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IS41LV16100A
EARLY WRITE CYCLE (OE = DON'T CARE)
ISSI
tRCtRAStRP®
RAStCSHtCRPtRCDtRSHtCAStCLCHUCAS/LCAStARtRADtASRtRAHtASCtRALtCAHtACHADDRESSRowColumntCWLtRWLtWCRtWCStWCHtWPRowWEtDHRtDStDHI/OValid DataDon’t CareIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
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IS41LV16100A
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
ISSI
tRWCtRAStRP®
RAStCSHtCRPtRCDtRSHtCAStCLCHUCAS/LCAStARtRADtASRtRAHtASCtCAHtACHtRALADDRESSRowtRCSColumntRWDtCWDtAWDRowtCWLtRWLtWPWEtAAtRACtCACtCLZtDStDHI/OOpentOEValid DOUTtODValid DINOpentOEHOEUndefinedDon’t Care12Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
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IS41LV16100A
EDO-PAGE-MODE READ CYCLE
ISSI
tRASPtRP®
RAStCSHtCRPtRCDtCAS, tCLCHtPC(1)tCAS, tCPtCLCHtRSHtCPtCAS, tCLCHtCPUCAS/LCAStARtRADtASRtASCtCAHtASCtCAHtASCtRALtCAHADDRESSRowtRAHtRCSColumnColumnColumntRCHRowtRRHWEtAAtRACtCACtCLZtCACtCOHtAAtCPAtCACtCLZtAAtCPAtOFFI/OOpentOEtOESValid DataValid DatatOEHCtODtOESValid DatatOEOpentODOEtOEPUndefinedDon’t CareNote:
1.tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the tPC specifications.
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IS41LV16100A
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASPISSI
tRPtRHCPtCSHtPCtCAS, tCLCHtCPtCAS, tCLCHtCPtRSHtCAS, tCLCHtACHtRALtCAHtCP®
RAStCRPtRCDUCAS/LCAStARtRADtASRtASCtACHtCAHtASCtACHtCAHtASCADDRESSRowtRAHColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPColumntCWLtWCStWCHtWPRowWEtWCRtDHRtDStDHtDStDHtDStDHtRWLI/OOEValid DataValid DataValid DataDon’t Care14Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
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IS41LV16100A
ISSI
tRASPtRP®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
RAStCSHtCRPtRCDtCAS, tCLCHtCPtPC / tPRWC(1)tCAS, tCLCHtCPtRSHtCAS, tCLCHtCPUCAS/LCAS tARtASRtRAHtRADtASCtRALtCAHtASCtCAHtASCtCAHADDRESSRowtRWDtRCSColumntCWLtWPtAWDtCWDColumntCWLtWPtAWDtCWDColumntRWLtCWLtWPtAWDtCWDRowWEtRACtCACtCLZ tAAtDStDHtAAtCPAtCACtCLZ tDStDHtAAtCPAtCACtCLZ tDHtDSI/OOpentOE DOUTDINtOD tOE DOUTDINtOD tOE DOUTDINtOD tOEH OpenOEUndefinedDon’t CareNote:
1.tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the tPC specifications.
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IS41LV16100A
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE)
ISSI
tRASPtRP®
RAStCSHtPCtCRPtRCDtCAStCPtCAS tPC tCPtRSHtCAStCPUCAS/LCAS tARtASRtRAHtRADtASCtCAHtASCtCAHtASCtACHtRALtCAHADDRESSRowtRCSColumn (A)Column (B)tRCHtWCSColumn (N) tWCHRowWEtRACtCACtAAtCPAtCACtCOH tAAtWHZtDStDHI/OOpentOE Valid Data (A)Valid Data (B)DINOpenOEDon’t Care16Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
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IS41LV16100A
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
ISSI
®
RAStCSHtCRPtRCDtCAStCPUCAS/LCAStARtRADtASRtRAHtASCtCAHtASCADDRESSWERowtRCSColumntRCHtAAtRACtCACtCLZtRCSColumntWHZtCLZI/OOEOpentOEValid DataOpentODUndefinedDon’t CareRAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRCtRAStRPRAStCRPtRPCUCAS/LCAStASRtRAHADDRESSI/ORowOpenRowDon’t CareIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
17
元器件交易网www.cecb2b.com
IS41LV16100A
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
ISSI
tRPtRAStRPtRAS®
RAStRPCtCPtCHRtCSRtRPCtCSRtCHRUCAS/LCASI/OOpenHIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAStRPtRASRAStCRPtRCDtRSHtCHRUCAS/LCAStARtASRtRADtRAHtASCtRALtCAHADDRESSRowColumntAAtRACtCACtCLZtOFF(2)I/OOpentOEtORDValid DataOpentODOEUndefinedDon’t CareNotes:
1.A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.2.tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
元器件交易网www.cecb2b.com
IS41LV16100A
ORDERING INFORMATION : 3.3VCommercial Range: 0°C to +70°C
Speed (ns)
50
Order Part No.IS41LV16100A-50KIS41LV16100A-50KLIS41LV16100A-50TIS41LV16100A-50TLIS41LV16100A-60KIS41LV16100A-60KLIS41LV16100A-60TIS41LV16100A-60TL
Package
400-mil SOJ
400-mil SOJ, Lead-free400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free400-mil SOJ
400-mil SOJ, Lead-free400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
ISSI
®
60
Industrial Range: -40°C to +85°C
Speed (ns)
50
Order Part No.IS41LV16100A-50KIIS41LV16100A-50KLIIS41LV16100A-50TIIS41LV16100A-50TLIIS41LV16100A-60KIIS41LV16100A-60KLIIS41LV16100A-60TIIS41LV16100A-60TLI
Package
400-mil SOJ
400-mil SOJ, Lead-free400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free400-mil SOJ
400-mil SOJ, Lead-free400-mil TSOP (Type II)
400-mil TSOP (Type II), Lead-free
60
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B03/02/05
19
元器件交易网www.cecb2b.com
PACKAGING INFORMATION
400-mil Plastic SOJPackage Code: KISSI
Notes:1. Controlling dimension: millimeters.2. BSC = Basic lead spacing between centers.3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.4. Reference document: JEDEC MS-027.®
N N/2+1E1E1N/2DASEATING PLANEbCA2eBA1E2MillimetersInchesMillimetersInchesMillimetersInchesSymbolMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxNo. Leads (N)283236A3.253.750.1280.1483.253.750.1280.1483.253.750.1280.148A10.64 —0.025 —0.64 —0.025 —0.64 —0.025 —A22.08 —0.082 —2.08 —0.082 —2.08 —0.082 —B0.380.510.0150.0200.380.510.0150.0200.380.510.0150.020b0.660.810.0260.0320.660.810.0260.0320.660.810.0260.032C0.180.330.0070.0130.180.330.0070.0130.180.330.0070.013D18.2918.540.7200.73020.8221.080.8200.83023.3723.620.9200.930E11.0511.300.4350.44511.0511.300.4350.44511.0511.300.4350.445E110.0310.290.3950.40510.0310.290.3950.40510.0310.290.3950.405E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSCe 1.27 BSC 0.050 BSC1.27 BSC 0.050 BSC1.27 BSC 0.050 BSCCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.F10/29/03
元器件交易网www.cecb2b.com
PACKAGING INFORMATION
ISSI
®
MillimetersInchesMillimetersInchesMillimetersInchesSymbolMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxNo. Leads (N)404244A3.253.750.1280.1483.253.750.1280.1483.253.750.1280.148A10.64 —0.025 —0.64 —0.025 —0.64 —0.025 —A22.08 —0.082 —2.08 —0.082 —2.08 —0.082 —B0.380.510.0150.0200.380.510.0150.0200.380.510.0150.020b0.660.810.0260.0320.660.810.0260.0320.660.810.0260.032C0.180.330.0070.0130.180.330.0070.0130.180.330.0070.013D25.9126.161.0201.03027.1827.431.0701.08028.4528.701.1201.130E11.0511.300.4350.44511.0511.300.4350.44511.0511.300.4350.445E110.0310.290.3950.40510.0310.290.3950.40510.0310.290.3950.405E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSCe 1.27 BSC 0.050 BSC1.27 BSC 0.050 BSC1.27 BSC 0.050 BSCCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. F10/29/03
元器件交易网www.cecb2b.com
PACKAGING INFORMATION
Plastic TSOPPackage Code: T (Type II)ISSI
N/2+1®
NE1ENotes:1.Controlling dimension: millimeters, unless otherwisespecified.2.BSC = Basic lead spacing between centers.3.Dimensions D1 and E do not include mold flash protru-sions and should be measured from the bottom of thepackage.4.Formed leads shall be planar with respect to one anotherwithin 0.004 inches at the seating plane.1DN/2ASEATING PLANEebA1LαcPlastic TSOP (T - Type II) (MS 25)MillimetersInchesSymbolMinMaxMinMaxRef. Std.N24/26A1.200.0472A10.050.150.0020.0059b0.300.510.0120.0201c0.120.210.0050.0083D17.0117.270.6700.6899E17.497.750.2950.3051e1.27 BSC0.050 BSCE9.029.420.4620.4701L0.400.600.0160.0236α0°5°0°5°Plastic TSOP (T - Type II) (MS 24)MillimetersInchesSymbolMinMaxMinMaxRef. Std.N40/44A1.200.0472A10.050.150.0020.0059b0.300.450.0120.0157c0.120.210.0050.0083D18.3118.510.7210.7287E110.0610.260.3960.4040e0.80 BSC0.031 BSCE11.5611.960.4550.4709L0.400.600.0160.0236α0°8°0°8°Plastic TSOP (T - Type II) (MS 24)MillimetersInchesSymbolMinMaxMinMaxRef. Std.N44/50A1.200.0472A10.050.150.0020.0059b0.300.450.0120.0157c0.120.210.0050.0083D20.8521.050.8210.8287E110.0610.260.3960.4040e0.80 BSC0.031 BSCE11.5611.960.4550.4709L0.400.600.0160.0236α0°8°0°8°Integrated Silicon Solution, Inc.PK13197T40 Rev. C 08/013/99
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