Cache memory circuit capable of processing a read

专利名称：Cache memory circuit capable of processing

a read request during transfer of a datablock

发明人：Kofuji, Masatoshi申请号：EP86101357.1申请日：19860203公开号：EP0189944B1公开日：19930512

摘要：In a cache memory circuit responsive to a read request to fetch a data block byblock transfer from a main memory to a cache memory when the data block is not storedin the cache memory, a sequence of data units into which the data block is divided issuccessively assigned to a plurality of cache write registers one by one. The assigned dataunits are simultaneously moved to one of sub-blocks of the cache memory during eachof write-in durations with an idle interval left between two adjacent ones of the write-indurations. Each state of the sub-blocks is monitored in a controller. During the idleinterval, a following read request can be processed with reference to the states of thesub-blocks even when it requests the data block being transferred. In addition, a readaddress for the following read request may be preserved in a saving address register toprocess another read request (Figure 1).

申请人：NEC CORPORATION

地址：7-1, SHIBA 5-CHOME MINATO-KU; TOKYO 108-01

代理机构：VOSSIUS & PARTNER

更多信息请下载全文后查看